Motorola Corporation

Freescale Semiconductor,inc.

Moshe Tarrab

Eran Pisek

Eytan Engel

Yossi Amon

Brett L Lindsley

Eliezer Weitz

Thomas J Kundmann

Uri Dayan

Natan Baron

Mack Mansouri

Yehuda Shaik

David Moshe

Mark Elnekave

Jacob Tokar

Dan Kuzmin

Leonid Belotserkovsky

Eli Borowitz

A device and method for performing SISO decoding. The method comprising the steps of: (a) providing a trellis representative of an output of a convolutional encoder, the convolutional encoder has a coding rate of R, the trellis having a block length T. (b) assigning an initial conditions to each starting node of the trellis for a forward iteration through the trellis. (c) computing a forward metric for each node, starting from the start of the trellis and advancing forward through the trellis and storing forward metrics of nodes of a plurality of starting stages of windows. (d) repeating stages d(1)-d(3) until all lambdas of the trellis are calculated; d(1) retrieving forward metrics of nodes of a starting stage of a window, the retrieved forward metrics were computed and stored during step (c). d(2) computing and storing forward metrics for each node, starting from a second stage of the window and ending at the ending stage of the window. d(3) computing backward metrics for each node, starting from the ending stage of the window and ending at the starting stage of the window; wherein when backward metrics of nodes of a stage are computed and the forward metrics of the nodes of an adjacent stage were previously computed, the computation of backward metrics is integrated with the computation of lambda from the stage to the adjacent stage and a storage of the calculated lambdas.

Apparatus and method for performing SISO decoding

A filter comprising of an internal memory for storing data and coefficients; an address generation unit, for generating memory addresses; a multiply and accumulate unit (i.e.&mdash;MAC unit), for performing multiply and accumulate functions. The filter can operate in a plurality of modes, such as multiple or single channel FIR filtering; multiple or single channel IIR filtering; multiple or single channel echo cancellation; multiple or single channel decimation and multiple or single channel extrapolation.

Multi channel filtering device and method

An electronic apparatus receives a noisy signal and produces and stores hard data and soft data. It has a first portion ( ) for receiving electromagnetic signals and producing hard data and soft data, and a second portion ( ) for storing soft data and hard data concerning a particular signal at a single location in a memory bank ( ), preferably at the same memory address. Hard data and soft data can be stored in consecutive memory cells. Hard data can overlap soft data. If hard data overlaps soft data, it preferably overlaps soft data least significant bits. The second portion ( ) has a memory bank ( ), a controller ( ) and also can have a synchronizer ( ) for synchronizing between soft data and hard data concerning the same input signal.

Electronic apparatus and method for receiving noisy signals

The present invention provides a task scheduling accelerating method, device and article of manufacture for determining and controlling multi-tasking. The device includes a synchronous task command interface for receiving commands from tasks on the host processor; an asynchronous task command interface for receiving commands from tasks and interrupt service routines on the host processor; an interrupt service routine interface for specifying and controlling a task switch; a semaphore post queue interface for specifying and determining a status of a data queue stored in the host processor; a status register for specifying a status of the task scheduling accelerator device; a computational unit for computing task scheduling decisions; and a bus for moving data between registers/interfaces and the computational unit.

Method, device and article of manufacture for implementing a real-time task scheduling accelerator

A finite impulse response filter (,) has a data memory bank (,) for storing data vectors and a coefficient memory bank (,) for storing coefficient vectors. Filtering is done by multiplying data words by coefficient words, and summing the results. The finite impulse response filter (,) operates in different modes, according to the type of data vector and coefficient vector. In two modes of operation consecutive elements of the data vector (,) are stored in consecutive odd memory words (,) within the data memory bank (,). In other modes consecutive elements of the data vector are stored in consecutive memory words (,) in the data memory bank (,). Consecutive coefficient vector elements (,) are stored in the consecutive memory words (,) in coefficient memory bank (,), wherein coefficient elements can be stored in reverse or forward order. The data memory bank (,) is coupled to a data address generator (,) comprising of counter (,), two multiplexers (,), a XOR gate (,) and an AND gate (,).

Finite impulse response filter and method

The present invention relates to memory and methods for storing/retrieving data in/from the memory that is accessed by at least two distinct data uses of different actual word widths. A memory for storing addressable binary data comprises a data storage organized in rows and columns of bit array cells, row address decoder and driver for addressing a selected row of bit array cells, column drivers for driving selected columns of bit array cells, and a bus switch port for selectively transferring data between the data storage and a first data bus with a first bus word width p and a second data bus with a second bus word width q smaller than the first bus word width p.

Multi bus access memory

According to the present invention, an LFSR (300) has a propagation path (30) of serially coupled stages (65) and gates (80-3, 80-4), a feedforward path (10) of gates (80-1) and a feedback path (20) of gates (80-2). Depending on control signals (P, B, M), the gates (80-1, 80-2, 80-3, 80-4) are either active gates and operate as xor-gates or passive gates and operate as transfer gates. Feedforward and feedback signals are derived from input and output signals and can be supplied to any stage (65), so that characteristic polynomials of the input-output function are variable. The LFSR can fully or partly operate as a TYPE 1 or TYPE 2 LFSR which enables the execution of different algorithms on one hardware base.

Signal processing apparatus with stages in a signal path operating as

The present invention relates to multi-bit exclusive-or (XOR) gates (60), including those where N parallel input bits (36, 38) are XORed with one data input bit (52). A modular approach is made using only one basic cell (30) for various implementations with different propagation delays. An N-bit XOR comprises basic cells (30) of adjacent first and second XOR gates (32, 34). Each first XOR gate (32) processes as input two of said N primary input bits (36, 38) and each second XOR gate (34) processes as input bits output bits of first or second XOR gates (32, 34) or the input data bit (52). This structure makes it possible to create an array of identical basic cells which is very suitable for VLSI implementation. There are few lines of connections between the different cells in the cell array which leads to substantial reduction in propagation delay without adding substantial wiring or layout complexity.

Multi-bit exclusive or

A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.

Filter co-processor

A method for ensuring CRC error generation by a data communication station after a transmitter exception such as an underrun whereby a parity bit is preset to a binary one, and toggled in response to successive binary ones of a serial bit stream. Each byte of the serial bit stream is transmitted sequentially. If a transmitter exception occurs, the byte before the exception is transmitted normally. However, only the first seven bits of the last byte are transmitted. The parity bit is sent as an eighth bit of the last byte, ensuring odd parity for the previous bit stream. Thereafter, a byte even parity is sent to assure that the overall message has odd parity. A receiving station interprets two consecutive bytes having the predetermined data pattern as the CRC, thus ensuring that the receiving station will reject the frame.

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Holon, Israel

Moshe Tarrab