Zikbit Ltd.

National Semiconductor Corporation

Mikamonu Group Ltd.

Facebook, Inc.

Facebook Technologies, LLC

Qimonda Ag

2Sens Ltd.

Moshe Meyassed

Avidan Akerib

Eli Ehrman

Oren Agam

Alexander Kalnitsky

Nadav Grossinger

Nitay Romano

Itai Derman

Kobi Kaminitz

Yair Alpern

Josh Meir

Marcelo Krygier

Osnat Goren-Peyser

Elad Amir

A device connectable to a near eye display or to a virtual reality headset and to a portable computing platform having a processor is provided herein. The device may include: an illuminator configured to illuminate a proximity of a user wearing the headset or the near eye display with patterned light; and an TR camera configured to capture reflections of said patterned light coming from at least one object located in the proximity of the user, wherein the processor is configured to: establish data and power connection between the device and said poliable computing platform and said near eye display; and generate a depth map of said object based on the reflections.

System, device and method for providing user interface for a virtual reality environment

A device system and methods comprising receiving a stereoscopic video or image of a scene including two perspective data streams (e.g. left and right) captured for example by a stereoscopic sensing device and analyzing the received stereoscopic video or image to yield stereoscopic discomfort data to assist a user to capture a stereoscopic 3D video of the scene, the stereoscopic discomfort data associated with discomfort effects such as dizziness, nausea, and eye stress.

System device and methods for assistance in capturing stereoscopic video or images

A device connectable to a near eye display or to a virtual reality headset and to a portable computing platform having a processor is provided herein. The device may include: an illuminator configured to illuminate a proximity of a user wearing the headset or the near eye display with patterned light; and an IR camera configured to capture reflections of said patterned light coming from at least one object located in the proximity of the user, wherein the processor is configured to: establish data and power connection between the device and said portable computing platform and said near eye display; and generate a depth map of said object based on the reflections.

A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.

Charge sharing in a TCAM array

A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern.

Using storage cells to perform computation

A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells.

A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory.

System, method and apparatus for memory with embedded associative section for computations

An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.

An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.

According to some embodiments of the present invention, a multi-protocol non-volatile memory ('NVM') card may include a NVM array, at least two protocol units, and a controller adapted to provide an external application access to the NVM array with the use of one of the protocol units. The controller or control logic may select which protocol unit to use based on a signal or other indicator of the protocol used by the external application. According to some embodiments of the present invention, a method of operating a multi-protocol memory card may include switching between a first and a second protocol or mode of the card based on a signal from an application attempting to access to the NVM card.

Multi-protocol memory card

The logic state stored in a memory cell having a Frohmann-Bentchkowsky p-channel memory transistor and a n-channel MOS access transistor is read by a sense amplifier which senses the magnitude of the current output from the memory cell during a read operation. The sense amplifier controls the voltage drop across the memory transistor and the access transistor (and a switching transistor) which, in turn, allows the difference in the magnitudes of the current from the programmed and unprogrammed cells to be optimized.

Memory device with sense amplifier that sets the voltage drop across the

The unintentional programming of a memory cell having a Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor, which can occur during a read operation when high read voltages are used, is eliminated by forming a diode-connected MOS transistor in parallel with the access transistor. The diode-connected transistor is formed to be off when an unprogrammed memory transistor is read, and to be on when a programmed memory transistor is read.

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Kadima, Israel

Moshe Meyassed