Intel Corporation

Moshe Maury Bach

Boris Ginzburg

Konstantin Levit-Gurevich

Esfir Natanzon

Gadi Haber

Igor Breger

Aya Elhanan

Ali-Reza Adl-Tabatabai

Bratin Saha

Yang Ni

Ady Tal

Jeffrey V Olivier

Sion Berkowits

James Henry Cownie

Adam Welc

Adam Wele

Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation

A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system

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Haifa, Israel

Moshe Maury Bach