Intel Corporation

Moshe Maor

Yaniv Fais

Michael Behar

Howard C Herbert

Roni Rosner

Zigi Walter

Oren Agam

Ronen Gabbai

Shay Gueron

Ittai Anati

Jacob Doweck

Vincent J Zimmer

David M Durham

Michael A Rothman

Uday R Savagaonkar

Carlos V Rozas

Edward Thomas Grochowski

Francis X Mckeen

Alex Nayshtut

Omer Ben-Shalom

Daniel Nemiroff

Gideon Gerzon

Ehud Cohen

Nimrod Diamant

Zvika Greenfield

Amber D Huffman

Bo A Zhang

Carey W Smith

Alex Berenzon

Edwin Jan Van Dalen

Ofir Mulla

Oron Lenz

Steven Roos

Martinus C Wezelenburg

Sergei Goffman

Tevi Devor

Yoram Zahavi

Fran Corrado

Ashutosh Parkhi

An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.

Methods and apparatus to tile walk a tensor for convolution operations

Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

Methods and apparatus to configure heterogenous components in an accelerator

A convolutional neural network (CNN) accelerator, including: a CNN circuit for performing a multiple-layer CNN computation, wherein the multiple layers are to receive an input feature according to an input feature map (IFM) and a weight matrix per output feature, wherein an output of a first layer provides an input for a next layer; and a mapping circuit to access a three-dimensional input matrix stored as a Z-major matrix; wherein the CNN circuit is to perform an inner-product direct convolution on the Z-major matrix, wherein the direct convolution lacks a lowering operation.

Inner product convolutional neural network accelerator

Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload

Apparatus, systems, and methods for a generic firmware-based kernel library mechanism are disclosed. An example apparatus includes a compiler to compile kernels into an executable and linkable format, an image generator to generate library images from executable and linkable format locations, a reducer to retrieve a library image, the library image retrieved starting from a first section of an existing library, the retrieved library image to be used as a platform for developing a new kernel library, a selector to select kernels to include in the new kernel library, one or more libraries organized into a defined number of kernel banks, the kernels combined based on intended application development, and a linker to link a library start function pointer to the library start function, the library start function positioned within the library image, the pointer incorporated in a first section of the library image.

Methods, systems, and apparatus for a generic firmware-based kernel library mechanism

Methods and apparatus to implement efficient communications between components of computing systems are disclosed. An example apparatus includes a message generator to: add a first value associated with a first field of a message to a shift register based on a first push operation, the message including multiple fields, at least two of the fields having different bit widths; and add a second value associated with a second field of the message to the shift register based on a second push operation, the second value to be adjacent the first value in the shift register in accordance with a structure of the message. The example apparatus further includes a communications interface to transmit content stored in the shift register to a hardware device via a bus having a width corresponding to a width of the shift register, the content including the message.

Methods and apparatus to implement efficient communications between components of computing systems

A processor device is provided with hardware-implemented logic to receive an instruction including a pointer identifier and a pointer change value, the pointer identifier including a pointer address field encoded with an address of a line of memory corresponding to a location of a pointer of a particular one of the one or more cyclic buffers, one or more cushion bits, and a buffer identifier field encoded with a buffer identifier assigned to the particular cyclic buffer. The logic further enables the processor to identify that the instruction is to apply to the particular cyclic buffer based on the buffer identifier, determine that the pointer change value causes a wraparound of the pointer in the particular cyclic buffer, and fix location of the pointer in the particular cyclic buffer based on the wraparound.

Cyclic buffer pointer fixing

A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.

Packed finite impulse response (FIR) filter processors, methods, systems, and instructions

Systems and methods may provide for establishing an out-of-band (OOB) channel between a local wireless interface and a remote backend receiver, and receiving information from a peripheral device via the local wireless interface. Additionally, the information may be sent to the backend receiver via the OOB channel, wherein the OOB channel bypasses a local operating system. In one example, a secure Bluetooth stack is used to receive the information from the peripheral device.

Integrating wireless input functionality into secure elements

Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for identifying and encrypting a subset of a plurality of instructions, for execution in a more secure execution environment. In various embodiments, the subset may include a single entry point and a single exit point. In various embodiments, one or more instructions of the plurality of instructions that precede or follow the subset may be executed in a first execution environment with a first security level. In various embodiments, the subset may be executed in a second execution environment with a second security level that is more secure than the first security level.

Identification and execution of subsets of a plurality of instructions in a more secure execution environment

This disclosure is directed to software modification that may be used to prevent software piracy and prevent unauthorized modification of applications. In some embodiments, a software vendor may modify software prior to distribution to a user. The software vendor may extract cutouts from an application to create a modified application. The modified application and the cutouts may be downloaded by a user device. The user device may run the application using the modified application and by executing the cutouts in a secure execution environment that conceals the underlying code in the cutouts.

Software modification for partial secure memory processing

Growing community of inventors

Kiryat Mozking, Israel

Moshe Maor