Sony Corporation

Sony Electronics Inc

Other

Sony Electronics Inc., Jointy

Moshe Bublil

Shirish C Gadre

Taner E Ozcelik

Subroto Bose

John Hong

Quang C Phung

Sabyasachi Dutta

A variable length decoder (VLD) for decoding MPEG-1 and -2 syntax compliant video bit streams. The VLD includes a micro-sequencer and VLD command decode/execution unit for controlling the MPEG decoding process using a novel instruction set. The instruction set includes a set of commands for decoding the video data and a set of flow control instructions. A rotator/barrel shifter is provided for making a predetermined number of encoded bits from the video bit stream available to the VLD and a variable length table decoder for variable length decoding using the MPEG standard variable length code (VLC) tables. The variable length table decoder shares a prefix pattern matching scheme across all of the VLC tables and organizes the variable length codes into a series of subtables. Each subtable corresponds to one of the unique prefix patterns. Variable length codes are decoded by identifying a leading pattern in the video data bit stream and, in parallel, accessing the subtable corresponding to that leading pattern. Run-length and amplitude level DCT coefficient symbols are stored in compressed form, and decoded as needed by an inverse transform unit. Motion vectors are also stored until needed by a motion compensation unit.

Variable length decoder for decoding digitally encoded video signals

A special purpose reduced instruction set central processing unit (RISC CPU) for controlling digital audio/video decoding. The instruction set includes flow control instructions which incorporate immediate values, used to jump over a small number of instructions, and other instructions used for larger jumps. Also, instructions obtain data from the video decoder of the ASIC in a streamlined fashion, using video decoder addresses hard-coded into the RISC CPU. Further instructions perform manipulations of individual bits of registers used as state/status flags. The RISC CPU includes watchdog functions for monitoring the delivery of data to the RISC CPU from other functional units or from memory, so that the RISC CPU can execute instructions while delivery of data from memory or other functional units is pending, unless that data is necessary for program execution, in which case, program execution stalls until the data arrives. To further reduce instruction latency, if an instruction makes use of the contents of a register that is in the process of being written by an immediately preceding instruction, the RISC CPU 'bypasses' the register file, using previous results directly in a subsequent instruction. For the purposes of control and debugging, the PC can be read or written by an external host, and instructions can be loaded directly from the host. Also, pages of instructions can be loaded to or from the instruction memory to allow for an unlimited virtual instruction memory space.

Special purpose processor for digital audio/video decoding

A CPU interface having an 8-bit mode in which the interface is capable of interfacing with a host CPU having 8-bit data bus, and a 16-bit mode in which the interface is capable of interfacing with a host CPU having a 16-bit data bus. The host CPU interface is further capable of switching between its 8-bit and 16-bit modes in real time in response to a 16-bit host CPU entering sections of 8-bit or 16-bit software. The interface also has 'direct' and 'indirect' addressing modes, so that the interface can send or receive time-multiplexed data, and receive address information on a single bus ('indirect' mode) or send or receive data, and receive address information in parallel on separate buses ('direct' mode).

ASIC having flexible host CPU interface for ASIC adaptable for multiple

A decoding circuit for decoding (or decompressing) compressed video data includes an RL circuit, such as MPEG encoded video data. The RL circuit includes a buffer memory for storing run-level pairs during the decoding process. Because the buffer memory in the RL circuit can store ran-level pairs, Huffman-decoding and header decoding, performed by a variable length decoding (VLD) circuit, is decoupled from inverse discrete transform decoding, performed by an IDCT circuit. This decoupling speeds up the decoding pipeline by allowing more continuous operation by both the VLD and IDCT circuits.

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Sunnyvale, CA, United States of America

Moshe Bublil