Qualcomm Incorporated

Mosaddiq Saifuddin

Jung Pill Kim

Xiangyu Dong

Dexter Tamio Chun

Jungwon Suh

Yanru Li

Deepti Vijayalakshmi Sriramagiri

Pankaj Deshmukh

Behnam Dashtipour

Victor Van Der Veen

David Hartley

SankaraRao Kunapareddy

Stanley Seungchul Song

Choh Fei Yeap

Sungryul Kim

Niladri Mojumder

Pratik Patel

Keunsoo Roh

Chun Xiang He

Nicholas Ambur

Jeremy Haugen

A DRAM memory controller is provided that identifies a marker command directed to a given row in a DRAM. If a threshold probability is satisfied in response to an identification of the marker command, the DRAM memory controller commands the DRAM to refresh a neighboring row in the DRAM. The neighboring row may be a neighboring of the given row or of a recently-closed row.

DRAM with quick random row refresh for rowhammer mitigation

An effect known as 'rowhammer' may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window may be counted and compared with a threshold. When it is detected that the number of row activation commands within the refresh window exceeds the threshold, an additional refresh command may be provided to the DRAM.

Dynamic random access memory (DRAM) row hammering mitigation

Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.

DRAM access in self-refresh state

A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

Method and apparatus for in-system management and repair of semi-conductor memory failure

In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.

Controlling a refresh mode of a dynamic random access memory (DRAM) die

Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.

Systems and methods for reducing memory failures

A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.

Bit remapping system

A static random-access memory (SRAM) array includes a first metal layer and a second metal layer. The metal layer includes multiple first source lines spanning multiple columns of cells. The multiple first source lines include a first source line and a second source line. The second metal layer includes multiple second source lines spanning multiple rows of cells. The SRAM array further includes a set of vias coupled to the multiple first source lines and to the multiple second source lines. A first via of the set of vias is coupled to the first source line and multiple vias of the set of vias are coupled to the second source line. Two vias of the multiple vias that are closest to the first via are each substantially the same distance from the first via.

Static random-access memory (SRAM) array

A method of performing refresh operations on a storage device includes identifying word lines coupled to weak storage elements. The method also includes grouping a plurality of word lines having distinct bank offsets onto a single refresh address. Each of the plurality of word lines is coupled to a corresponding weak storage element. The method further includes performing a refresh of the single refresh address.

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San Diego, CA, United States of America

Mosaddiq Saifuddin