Apple Inc.

Marvellworld Trade Ltd.

Morteza Nick

David M Signoff

Krishna Chaitanya Reddy Gangavaram

Kefei Wu

Voravit Vorapipat

Renaldi Winoto

Antonio Passamani

Fei Wang

Xiang Guan

Song Hu

Anuranjan Jha

Preeti S Mulage

This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.

Variable gain amplifier with subthreshold biasing

Radio frequency (RF) transmitters of a device (aggressor device) may unintentionally transmit a high-power output signal to antennas of a receiving device (victim device). In some RF systems, a victim device may have no or little protection between its antennas and transistors in an integrated circuit. Performance or lifetime of the transistors may be negatively impacted due to large voltage swings that may result from the high-power signal received from the aggressor device. To prevent or mitigate impact to performance or lifetime of the transistors due to the large voltage swings, protection circuitry including switches and a direct current (DC) power source (e.g., a charge pump) may be implemented at an input of a receiver of the victim device to shunt the power from sensitive circuit components of the victim device.

Charge pump-enabled circuit protection switch

Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/− and I/Q) component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.

Accurate sign change for radio frequency transmitters

Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/&#x2212; and I/Q component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.

A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.

High efficiency switching power amplifier

Systems and techniques relating to wireless communication devices and reconfigurable an integrated RF Front-End for dual-band WLAN transceivers include, according to an aspect, an integrated circuit chip comprising: radio frequency (RF) Front-End circuitry, wherein the RF Front-End circuitry comprises (i) an antenna input line configured to connect with one or more antennas of a wireless communication device, (ii) a transmitter input line, (ii) a first receiver output line, (iii) and a second receiver output line; harmonic trap circuitry coupled with the RF Front-End circuitry via the antenna input line, the harmonic trap circuitry being fully integrated on the integrated circuit chip.

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San Francisco, CA, United States of America

Morteza Nick