Broadcom Corporation

Intel Corporation

Novelics, LLC

Novelies, LLC

Norvelics, LLC

Morteza Cyrus Afghahi

Esin Terzioglu

Gil I Winograd

Mehdi Hatamian

Yueming He

Sami Issa

Bibhudatta Sahoo

Rajendran Nair

Mark A Beiley

Brent D Thomas

Matthew Vernon Kaufmann

Babak B Nikjou

Melinda L Miller

Matthew S Jones

Khalil Waleed

Issa Sami

Ramin Rajabian

In one embodiment, a die arrangement is disclosed in which a wire-bond pad may be operatively coupled to a power supply via a wire bond. A first pad may be operatively coupled to the wire-bond pad. A second pad may be operatively coupled to the first pad via a redistribution layer.

System and method for reducing voltage drops in integrated circuits

A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Single-ended sense amplifier with sample-and-hold reference

The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Block redundancy implementation in hierarchical rams

A non-volatile memory cell includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate.

Single-poly non-volatile memory cell

In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node.

Dense read-only memory

In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a 'repair true' signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.

Memory row and column redundancy

In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors.

Hybrid DRAM

In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of memory cells arranged into rows and columns, wherein each memory cell comprises an access transistor coupled to a storage transistor, each access transistor being arranged in a rectangular shape having a length greater than a width, the length being aligned with a corresponding column, the access transistor coupling to a storage transistor having a width greater than the width of the rectangular shape, the access transistor having a length aligned with a corresponding row such that each memory cell is L-shaped, and wherein the L-shaped memory cells in each column are staggered with respect to neighboring columns such that the L-shaped memory cells in a given column are interlocked with the L-shaped memory cells in an adjacent column.

DRAM architecture

In one embodiment, a memory is provided that includes: a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line; a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell coupled to a first one of the bit lines in the pair; and a first trim capacitor having a first terminal directly coupled to one of the bit lines in the pair, the first trim capacitor having an opposing second terminal coupled to a first trim capacitor signal, the memory being adapted to change a voltage of the first trim capacitor signal while the sense amplifier senses the voltage to determine the binary state of the accessed memory cell.

RAM with trim capacitors

In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of rows of memory cells, each of the memory cell rows being arranged into columns, wherein each of the memory cell rows is crossed by a row of four word lines, and wherein each of the columns is crossed by a bit line; a plurality of sense amplifiers corresponding to the bit lines such that a single sense amplifier corresponds to every four bit lines; and a plurality of 4:1 multiplexers corresponding to the plurality of sense amplifiers, each 4:1 multiplexer coupling its corresponding sense amplifier to its corresponding four bit lines.

DRAM with reduced power consumption

A one-time-programmable memory cell uses two complementary antifuses that are programmed in a complementary fashion such that only one of the two complementary antifuses is stressed by a programming voltage. The programming voltage stress one a particular one of the complementary antifuses indicates a logical state of the memory cell. For example, a logical high state may correspond to a first one of the complementary antifuses being stressed whereas a logical low state may correspond to the stressing of the remaining one of the complementary antifuses.

One-time-programmable memory

A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.

A CAM cell is provided that includes: an SRAM cell adapted to store a bit; a data line adapted to provide a corresponding comparand bit; an XOR gate adapted to XOR the stored bit and the comparand bit to provide an XOR output, and a switch adapted to close in response to the XOR output.

Low-power CAM cell

In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's memory cells matches a corresponding portion of a comparand word if an enable input for the ripple group is asserted, each complex logic gate asserting an output if the determination indicates a match, the ripple groups being arranged from a first ripple group to a last ripple group such that the output from the first ripple group's complex logic gate functions as the enable input for a second ripple group's complex logic gate and so on such that an output from a next-to-last ripple group's complex logic gate functions as the enable input for the last ripple group's complex logic gate.

Low-power CAM

In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.

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Coto de Caza, CA, United States of America

Morteza Cyrus Afghahi