Mips Technologies, Inc.

Mips Technology, Inc.

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Pascal Paillier

Jakob Schou Jensen

Jean-Francois Dhem

Kevin D Kissell

Michael Gottlieb Jensen

Hartvig W J Ekner

Soeren R F Laursen

Flemming Nygreen

Ole Kristian Friis

Kim Mostrup

Hartig W J Ekner

A microprocessor including random cache line refill ordering to lessen side channel leakage in a cache line and thus thwart cryptanalysis attacks such as timing attacks, power analysis attacks, and probe attacks. A random sequence generator is used to randomize the order in which memory locations are read when filling a cache line.

Random cache line refill

An interface between electronic devices uses a credit-based flow protocol with sustained bus signals. An initiating device waits for credit to issue a command to a target device. When credit is available, the initiating device issues the command to the target device such that the command is accessible by the target device until a new command is issued. The command may include a read or write request to the target device.

Interface with credit-based flow control and sustained bus signals

A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register ('MFLHXU') and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator ('MTLHX').

Extended precision accumulator

Polynomial arithmetic instructions are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction are provided.

Microprocessor instructions for performing polynomial arithmetic operations

A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations. To this end, the multiply unit may include an input data path that receives input operands, an arithmetic multiplier connected to receive the input operands, a binary polynomial multiplier having components separate and distinct from the arithmetic multiplier and connected to receive the one or more input operands, and a multiply unit output data path connected to receive an output of the arithmetic multiplier and connected to receive an output of the binary polynomial multiplier. The multiply unit also may include permutation logic that performs permutation operations on the input operands.

Binary polynomial multiplier

An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers. The ISA mode selection logic receives the particular address, and compares it against the plurality of address ranges to determine the particular ISA decoding mode for the particular program instruction.

Selection of ISA decoding mode for plural instruction sets based upon instruction address

A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be configurable so that the average frequency of random slips generated by the system may be set. Additional techniques are provided to make nullified instructions consume power like any other executing instruction.

Random slip generator

A microprocessor includes random cache line refill ordering to lessen side channel leakage in a cache line and thus thwart cryptanalysis attacks such as timing attacks, power analysis attacks, and probe attacks. A random sequence generator is used to randomize the order in which memory locations are read when filling a cache line.

Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier.

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Frederiksberg, Denmark

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