Synopsys, Inc.

Morten Christiansen

Dino Anthony Toffolon

Davit Petrosyan

Andrew Chung Chun Lam

A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low voltage levels, and the high-voltage PHY portion includes a driver circuit that retransmits the low-voltage data signals onto a bus at the required 3.3V level. Incoming 3.3V data signals pass through an attenuator circuit before being processed using a receiver circuit provided on the low-voltage PHY portion. In USB applications, outgoing USB High Speed data signals are generated by a driver circuit provided on a low-voltage USB PHY portion.

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Sunnyvale, CA, United States of America

Morten Christiansen