Axt, Inc.

Beijing Tongmei Xtal Technology Co., Ltd.

Morris Young

Weiguo Liu

Rajaram Shetty

Wei Zhang

Wen Wan Zhou

M Hani Badawi

Sungnee George Chu

Yuanli Wang

Vincent Wensen Liu

Davis Zhang

Methods and systems for low etch pit density gallium arsenide crystals with boron dopant may include a gallium arsenide single crystal wafer having boron as a dopant, an etch pit density of less than 500 cm, and optical absorption of 6 cmor less at 940 nm. The wafer may have an etch pit density of less than 200 cm. The wafer may have a diameter of 6 inches or greater. The wafer may have a boron concentration between 1×10cmand 2×10cm. The wafer may have a thickness of 300 μm or greater. Optoelectronic devices may be formed on a first surface of the wafer, which may be diced into a plurality of die and optical signals from an optoelectronic device on one side of one of the die may be communicated out a second side of the die opposite to the one side.

Low etch pit density gallium arsenide crystals with boron dopant

Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm, and a resistivity of 1×10Ω-cm or more. The wafer may have an optical absorption of less than 5 cmless than 4 cmor less than 3 cmat 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm/V-sec or higher. The wafer may have a thickness of 500 μm or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×10cmor less.

Low etch pit density 6 inch semi-insulating gallium arsenide wafers

Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cmor less, or 100 cmor less, or 10 cmor less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Low etch pit density, low slip line density, and low strain indium phosphide

Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm, and a resistivity of 1&#xd7;10&#x3a9;-cm or more. The wafer may have an optical absorption of less than 5 cmless than 4 cmor less than 3 cmat 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm/V-sec or higher. The wafer may have a thickness of 500 &#x3bc;m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1&#xd7;10cmor less.

A IIIA-VA group semi-conductor single crystal substrate () has one of or both of the following two properties: an oxygen content of 1.6&#xd7;10-5.6&#xd7;10atoms/cmin a range from the surface to a depth of 10 &#x3bc;m of the wafer, and an electron mobility of 4,800 cm/V&#xb7;s-5,850 cm/V&#xb7;s. Further, a method for preparing the semi-conductor single crystal substrate () comprises: placing a single crystal substrate () to be processed in a container (); sealing said container (), and keeping said single crystal substrate () to be processed at a temperature in the range of from the crystalline melting point &#x2212;240&#xb0; C. to the crystalline melting point &#x2212;30&#xb0; C. for 5 hours to 20 hours; preferably, keeping a gallium arsenide single crystal at a temperature of 1,000&#xb0; C. to 1,200&#xb0; C. for 5 hours to 20 hours.

IIIA-VA group semiconductor single crystal substrate and method for preparing same

Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density.

Low etch pit density (EPD) semi-insulating III-V wafers

A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer.

Growing community of inventors

Fremont, CA, United States of America

Morris Young