Intel Corporation

Morris Marden

Matthew C Merten

Avinash Sodani

Alexandre J Farcy

James Hadley

Ilhyun Kim

Glenn J Hinton

Stephan Jourdan

Per H Hammarlund

Robert S Chappell

Beeman C Strong

Douglas M Carmean

John G Holm

David W Burns

Sebastien Hily

Vijaykumar Balaram Kadgi

Laura A Knauth

Robert L Hinton

Prakash Math

Pierre Michaud

Santhosh Srinath

Joseph A McMahon

Grace C Lee

Fariborz Tabesh

A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.

Physical reference list for tracking physical register sharing

A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements

Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor

A method and apparatus for providing quality of service in a multi-processing element environment based on priority is herein described. Consumption of resources, such as a reservation station and a pipeline, are biased towards a higher priority processing element. In a reservation station, mask elements are set to provide access for higher priority processing elements to more reservation entries. In a pipeline, bias logic provides a ratio of preference for selection of a high priority processing element for further processing in the pipeline.

Providing quality of service via thread priority in a hyper-threaded microprocessor

Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

Decoupling the number of logical threads from the number of simultaneous physical threads in a processor

In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor coupled to the memory unit, and a controller coupled to the first and second counters to execute one or more one remediation measures with respect to the senior request based on a value of at least one of the counters. Other embodiments are described and claimed.

Detecting and resolving locks in a memory unit

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Hillsboro, OR, United States of America

Morris Marden