Intel Corporation

Chips and Technologies, Llc.

Morris E Jones, Jr

James A Picard

Arun Johary

Ying Cui

Carl L First

Zudan Shi

Chairong Li

Everitt Kwocktong Chock

Alak K Deb

Edward P Hutchins

Mahesh Siddappa

Pierre M Selwan

Yungha Y Han

David G Reed

A method and apparatus for video motion compensation, power of two reduction and color format conversion is disclosed. The motion compensation engine performs the MPEG-2 functions of half pel compensation, inverse discrete cosine transform and merge. Dual prime, field-based and frame-based macroblocks are supported. Data reduction may be performed in the vertical direction, the horizontal direction, or both.

Method and apparatus for video motion compensation, reduction and color formatting

A method and apparatus for horizontally expanding a video graphics adapter (VGA) text character display image to fully fill the screen of a flat panel display. Cell lines for each character are remapped to provide expanded cell lines. The flat panel apparatus includes a video memory for storing the character code, attribute data and font data, a character generator for generating character font data based on the character code, a lookup table for providing expanded cell lines, and an attribute controller for combining the font data and the attribute data for output to a flat panel display.

Method and apparatus for text image stretching

A system, apparatus, and method for depicting and responding to systematic problems and/or incidents in computing devices at a Basic Input/Output System level are described herein.

Bios-level incident response system and method

Methods and apparatus relating to computer system maintenance and/or diagnostics are described. In an embodiment, maintenance and diagnostics operations may be performed on a computer system during power-down modes, e.g., without disturbing the pre-power-down state of the computer system. In another embodiment, a request may be provided to perform a maintenance operation on a computer system in response to a power-down state of the computer system. Also, some contents of a state of the computer system may be stored in a memory in response to the at least some contents not previously having been backed-up in accordance with one embodiment. Other embodiments are also disclosed.

Computer system maintenance and diagnostics techniques

An apparatus for scalable image processing includes a display, multiple graphics functional units and a mode selector. Each of the graphics functional units has a configuration of a predetermined type to control the display. The mode selector determines which combination of graphics functional units controls the display. A method for scalable image processing includes monitoring at least one parameter, determining whether to switch from one graphics functional unit configuration to a new graphics functional unit configuration based upon one or more of the parameters, and switching to the new graphics functional unit configuration.

Method and apparatus for scalable image processing

A memory architecture for a video graphics controller includes a dynamic random access memory (DRAM), a static random access memory (SRAM) and a bus. The DRAM includes a data port, an address decoder that can receive an address to select a memory location in the DRAM and a command instruction bus that can receive instructions for data transfer. The SRAM includes a first data port to transfer data with the DRAM, a second data port to transfer data with other than the DRAM, a first address decoder that can receive an address to select a memory location in the SRAM for data transfer with the DRAM, a first read/write input that can receive a signal for data transfer with the DRAM, a second address decoder that can receive an address to select a memory location in a page of the SRAM to transfer data with other than the DRAM and a second read/write input that can receive a signal for data transfer from other than the DRAM. The bus is coupled between the data port of the DRAM and the first data port of the SRAM for data transfer between the DRAM and the SRAM.

Memory architecture for video graphics environment

The invention is an improved method and apparatus for implementing the &ldquo;least-recently-used&rdquo; (LRU) replacement algorithm in a memory. A counter keeps count of the number of memory accesses. Each block in the memory is associated with a time tag that represents an approximation of the age in the memory. The criteria for updating a time tag is based upon the value of the counter and the time tag. The block with a time tag value representing the highest residence time in memory with respect to the other time tags is always replaced first. The time tag for the most recently accessed block is set to a value representing the least residence time in memory and the other time tags are updated based upon their age in the memory.

Method and apparatus for approximated least-recently-used algorithm memory replacement

A method and apparatus for horizontally expanding a video graphics adapter (VGA) text character display image to fully fill the screen of a fiat panel display. Cell lines for each character are remapped to provide expanded cell lines. The flat panel apparatus includes a video memory for storing the character code, attribute data and font data, a character generator for generating character font data based on the character code, a lookup table for providing expanded cell lines, and an attribute controller for combining the font data and the attribute data for output to a flat panel display.

A system for performing input and output operations to and from a processor in which interrupts for I/O operations are conditionally generated internally rather than externally by (Super State.TM.) microcode residing in a separate address space in memory in an area protected from the user. A (superblock) register in the processor points to the Super State area in memory. If the Super State mode is turned on, an interrupt is generated within the processor whenever the control table allows. The interrupt directs the processor to the register and hence to the Super State code. By way of example, the Super State code controls power and access to the port, decides whether to put the interrupt in memory and emulate the I/O, and counts access to the port. The invention provides a processor with the flexibility of performing I/O operations to and from memory and/or to a peripheral or to trap an interrupt into a new operating environment for device emulation. Device emulation and monitoring is allowed without considerable program overhead. The invention provides a powerful, efficient I/O control system which can change or adapt in response the changing demands of an application program.

System for performing input and output operations to and from a processor

The present invention includes a memory clock system for a graphics controller including a plurality of clock pulse generators, and a clock controller which selects the clock frequency based on the state of the graphics controller functional units.

Graphics controller utilizing a variable frequency clock

A method and apparatus for improving bandwidth of sequential access to a display data memory. Display data and tag information related to consecutive data repetitions are stored. No display memory access is needed to output data to the CRT during the time periods when data is being repeated, thus increasing display memory bandwidth. Display data from a location in display memory is stored in a latch, and is output from the latch until the tag information indicates no more data repetitions occur.

Method and apparatus for performing run length tagging for increased

An efficient organization for microcoded instruction sets which have processor operations in which not all the bits of an instruction word are required. The organization has two registers for receiving and holding the first and second byte of instructions at a time, a first ROM connected to the register for decoding the first byte into control signals for operation of said microprocessor. One of these control signals is generated whenever the portion of the second instruction byte is required. The organization also has a second ROM connected to the register for decoding the portion of the second byte into control signals. Connected to said first and second ROMs is a multiplexer which selects the decoded second byte control signals for operation of the microprocessor responsive to the first ROM control signal. The combined size of the first and second ROMs is much smaller compared to that of a ROM which decodes both bytes all the time and achieves a great savings in the space occupied by the processor integrated circuit.

Growing community of inventors

Saratoga, CA, United States of America

Morris E Jones, Jr