Energy Conversion Devices, Inc.

Morrel H Cohen

Stanford R Ovshinsky

An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices. In a preferred embodiment, the output response is resistance and the error reduction circuit reduces errors or fluctuations in the resistance. The error reduction circuit includes a network of chalcogenide devices, each of which is nominally equivalent and each of which is programmed into the same state having the same nominal resistance. The inclusion of multiple devices in the network of the instant error reduction circuit provides for a reduction in the contributions of both dynamic fluctuations and manufacturing fluctuations to the error in the output response.

Error reduction circuit for chalcogenide devices

An electronic device for securing the contents of data storage and processing elements. The device includes a security element and a phase-change element connected in a parallel arrangement. The security element is a three-terminal device, having an ON state and an OFF state which differ in resistance and regulate electronic access to the phase-change element by controlling the flow of electrical current applied to the parallel combination. In the ON state, the resistance of the security element is less than that of the phase-change element, thereby precluding a determination of the resistance of the phase-change element. In this PROTECT mode, the contents of the phase-change element are secured. In the OFF state, the resistance of the security element is greater than that of the phase-change material so that the resistance of the parallel combination approaches that of the phase-change element. In this READ mode, the resistance and information content of the phase-change element can be determined.

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Bridgewater, NJ, United States of America

Morrel H Cohen