Fujitsu Corporation

Moriyuki Takamura

Masayuki Ikeda

Haruhiko Ueno

Shigeru Nagasawa

Naoki Shinjo

Kenichi Ishizaka

Kazushige Kobayakawa

Masami Dewa

Teruo Utsumi

Naoki Sueyasu

Takashi Ibi

Shigeru Mukasa

A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address. Data is transferred from a first one of the plurality of processors to a second one of the plurality of processors by writing the data into the storage of the second processor according to the global virtual address or the local virtual address of the second processor, the second processor is notified of the global virtual address or the local virtual address of the transferred data, the notified global virtual address or the notified local virtual address is then translated into the real address which corresponds to the notified global virtual address or the notified local virtual address, data is read from the storage of the second processor to the second processor according to the translated real address, and the read data is calculated in the second processor.

Multiprocessor system and parallel processing method for processing data

A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information. A processing shifting element shifts, when the group of processors are judged to be in synchronism, all the processors in the group to the next process of a program.

Synchronous processing method and apparatus for a plurality of

An error correcting and detecting system using a parity check H-matrix divided into a plurality of block vectors each including four or three column vectors each having eight elements. In the H-matrix, (i) there are no all '0' vectors; (ii) all column vectors are different from each other; (iii) 8 column vectors each having only one '1' is included therein, (iv) each column vector has an odd number of '1's'; (v) the modulo-2 sum of any three column vectors within any block never equals any column vectors of the H-matrix; (vi) the modulo-2 sum of four column vectors within any block never equals an all '0' vector; and (vii) the modulo-2 sum of eight column vectors within any two blocks never equals an all '0' vector.

Error correcting and detecting system

Growing community of inventors

Kawasaki, Japan

Moriyuki Takamura