Hitachi, Ltd.

Moritoshi Yasunaga

Noboru Masuda

Minoru Yamada

Masayoshi Yagyu

Mitsuo Asai

Katsunari Shibata

Hideo Todokoro

Yasunari Umemoto

Tohru Ishitani

Takehisa Hayashi

Hiroyuki Itoh

Tsuyoshi Ohnishi

Akira Masaki

Kenichi Ishibashi

Toshio Doi

Hirotoshi Tanaka

Keiichirou Nakanishi

Kazunori Kuriyama

Kazumichi Yamamoto

Tatsuya Saitoh

Ryotaro Kamikawai

Yuzo Hirai

Hiroaki Odawara

Masaaki Nishi

A data processor transfers files at high speeds from a magnetic disk or other storage media to a network and shortens the processing time for the file transfers. An I/O processor includes (i) a channel to which a magnetic disk is connected, (ii) a LAN adapter to which a network is connected, (iii) a switch for switching and connecting the channel and LAN adapter, and (iv) a channel controller for controlling the channel, the LAN adapter, and the switch. The channel controller controls the channel, the LAN adapter, and the switch in accordance with a data transfer start instruction from an instruction processor. The channel reads data from the magnetic disk and transfers it to the LAN adapter via the switch. The LAN adapter sends the data to the network or reads data from the network and transfers it to the channel via the switch. The channel sends the data to the magnetic disk.

Computer system with an input/output processor which enables direct file

An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden layer and the output layer executes a computation for externally input data to determine the values of outputs therefrom, and a backward network comprising the output layer and the hidden layer executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

Information processing apparatus

A semiconductor integrated circuit device includes a plurality of integrated circuit chips and a large-sized integrated circuit element on which the plurality of integrated circuit chips are mounted. The large-sized integrated circuit element includes a logic circuit for electrically interconnecting the integrated circuit chips mounted on it. The logic circuit provided within the large-sized integrated circuit element includes a control circuit for controlling a connection relation between the integrated circuit chips mounted on the large-sized integrated circuit element. Further, the logic circuit includes buffer or latch circuits for relaying signals transmitted between the integrated circuit chips.

Semiconductor integrated circuit device and computer system using the

An information processing apparatus which includes an input layer, a hidden layer and an output layer, and performs a computation in terms of models of neurons. A forward network, having the input layer, the hidden layer and the output layer, executes a computation for externally input data to determine the values of outputs therefrom, and a backward network, having the output layer and the hidden layer, executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

A device for generating voltage signals in a semiconductor device upon irradiation with a charged particle beam, wherein a circuit for converting a beam current of the irradiated charged particle beam into the voltage signals is constituted by a bipolar transistor and a load device contained in the semiconductor device, and a portion of the line pattern connected to the base of the bipolar transistor is irradiated with the charged particle beam, so that signals are generated at high speeds even by using a weak charged particle beam without permitting the device to be broken down.

Signal generator and method of generating signal voltages using the same

An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

Information processing system

A semiconductor integrated circuit device includes: input terminals; output terminals; a group of gates which receives an input signal applied to the input terminals and outputs an output signal from the output terminals, the output signal corresponding to the state of the input signal; and an arrangement for forcibly setting the output of each gate constituting the group either at a '1' level or at a '0' level irrespective of the state of the input signal and the state of an input signal to each gate. The arrangement for forcibly setting the output is an arrangement for changing the potential of a semiconductor substrate in which each gate is formed. This arrangement for changing potential includes an impurity doped region formed in the semiconductor substrate, the impurity doped region surrounding at least a transistor constituting each gate so as to apply a potential to the transistor, and a terminal for applying the potential to the impurity doped region. The semiconductor integrated circuit device according to another aspect includes an observation pad formed on a portion of at least one of the output and input areas of each gate, the observation pad being exposed without being covered with an insulator layer and the potential of the observation pad being observed as a difference of shading by using an electron or ion beam tester. A fault of each gate can be detected in accordance with a shading image of the observation pads.

Semiconductor integrated circuit device and method of testing the same

A connector structure comprising an electrically conductive plate having a plurality of through holes formed therein, an electrically insulated film formed on the inner wall of at least one of the through holes, an electrically conductive film formed on the inner wall of at least one other through hole, and an electrically conductive material of a low melting point provided within the through holes. The low melting point material provided in the through holes whose inner walls are coated with an electrically insulating film is insulated from the electrically conductive plate and such through holes may serve to receive signal propagating pins. The low melting point material in the through holes whose inner walls are coated with an electrically conductive film are tightly bonded to its inner wall due to the wettability between the low melting point material and the electrically conductive film so that such through holes may serve to receive a common potential pin to electrically stabilize the electrically conductive plate and to reduce electrical capacitance unnecessarily formed between the signal propagating pin receiving through holes. Thus, the connector structure is adapted for a high speed signal transmission without suffering substantial crosstalk noise.

Connector structure

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Kawaguchi, Japan

Moritoshi Yasunaga