Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Hitachi Global Storage Technologies Netherlands B.v.

Hitachi Medical Corporation

Hitachi Video Engineering, Incorporated

N.v. Philips' Gloeilampenfabrieken

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Video Eng. Inc.

Morishi Izumita

Seiichi Mita

Nobukazu Doi

Kazuhiro Sato

Toshiyuki Akiyama

Shusaku Nagahara

Masuo Umemoto

Yoshizumi Eto

Kenji Takahashi

Morito Rokuda

Terumi Takashi

Hiroto Yamauchi

Hidehiro Kanada

Mamoru Kaneko

Takeshi Maeda

Yoshito Tsunoda

Hiroyuki Tsuchinaga

Johannes W Bergmans

Naoki Ozawa

Akira Saito

Shigeyuki Ikeda

Hitoshi Katayama

Fumio Hara

Yasuyuki Itou

Tetsuya Amano

Shigeru Nakamura

Koji Kudo

Takuya Imaide

Yuan Xing Lee

Yoshinori Okada

Hideki Sawaguchi

Michio Masuda

Hiroshi Ide

Shinya Ohba

Masaru Noda

Yoshiju Watanabe

Masatoshi Ohtake

Shigeki Nishizawa

Masuo Kasai

Nobuo Murata

Hiroaki Nabeyama

Hideki Imai

Kazuyuki Takeshita

Yuichi Michikawa

Yasuo Inagaki

Masanori Sato

Susumu Kasai

Susumu Sawano

Masaharu Kondou

Hideaki Maeda

Hiroyuki Hanyu

Hiroshi Takayanagi

Hitoshi Takagi

Hiroshi Shiono

Yuuichi Michikawa

Masuo Umenoto

Fuyuki Inui

Shigeaki Fujino

Input data (A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file, an error detecting code is added in an error detection calculation circuit, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuitto record the data in a storage. In the reproduction, error correction in units of symbols is performed to reproduced data from the storagein an error correction circuit, error detection processing is performed in an error detection calculation circuit, and then data having the integral multiple of 8 bits is recovered in a register fileto output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Error detection and correction circuit and semiconductor memory

Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint. In one embodiment, a system for processing data comprises a maximum transition run or timing-varying maximum transition run (hereinafter MTR) encoder configured to encode input data sequence from a hard disk controller into an MTR coded sequence which satisfies a j-constraint; an error correction code (ECC) encoder configured to generate ECC check bits for the MTR coded sequence; and a bit-level interleaving and substitution module configured to interleave the generated ECC check bits into the MTR coded sequence by stuffing the generated ECC check bits at boundaries of MTR coded blocks of the MTR coded sequence, to determine if a violation of the j-constraint has occurred at the boundaries of the MTR coded blocks, and to perform substitution of bits at a boundary of the MTR coded blocks to maintain the j-constraint if a violation of the j-constraint has occurred.

Permuting MTR code with ECC without need for second MTR code

In one embodiment, a symbol error correction encoder effects block interleaving on recording data and thereafter performs first error correction encoding on the recording data. Next, a symbol error correction encoder performs encoding on the whole block. A reproducing processing circuit outputs likelihood information of respective bits. A first error correction decoder corrects a random error produced upon recording and reproduction, using the likelihood information. Since it is possible to make an improvement in performance with respect to the random error by repetitive decoding at this time, the post-correction data is returned to the reproducing processing circuit. After the completion of such repetitive processing, the data is digitized and subjected to an error correction in symbol unit by a hard determination, and outputted to a symbol error correction decoder.

Signal processing method and signal processing circuit

Embodiments of the invention allow relatively simple circuits to provide a coding device capable of coding longer bit-length data suitably for disk apparatus and a decoding device capable of decoding the data coded by the coding device. In one embodiment, a coding device comprises: a coder which, based on an M bits code string, produces an (M+1) bits coded string where each of the plural bits which may appear in the M bits code string is limited in run length; a preprocessor which produces an M bits code string by removing (N&#x2212;M) bits respectively from predefined (N&#x2212;M) positions of an incoming N bits code string and outputs the M bits code string to the coder; and a postprocessor which produces and outputs an (N+1) bits code string by inserting the (N&#x2212;M) bits, which are removed by the preprocessor, into predefined (N&#x2212;M) respective insertion positions of the (M+1) bits coded string output from the coder.

Coding device and decoding device

Embodiments of the invention a signal processing method capable of realizing low decoding error ratio by using a simple configuration free from unnecessary redundant bits. In one embodiment, user data (512 bytes+additional data) input to an input terminal is RLL-encoded by a RLL encoder. The data from the RLL encoderis entered into a symbol error correction encoder where 9-bit symbol encoding is done. Its RS code portion is RLL-encoded by a RLL encoder. Signal read from a magnetic disk is entered into a RLL decoderwhere the RS code portion is RLL-decoded. The signal from the RLL decoderis then entered into a symbol error correction decoder where random read/write errors, burst errors attributable to defects and other errors are corrected to produce a (user data+RLL) signal. This data is output to an output terminal after being decoded by a RLL decoder

Data processing method and circuit for data recording and reproducing and data recording and reproducing apparatus

Here is disclosed an information recording and reproducing apparatus comprising a multi-phase quadrature angular modulator for subjecting a signal to be written on a recording medium to multi-phase quadrature angular modulation to generate a modulated signal expressing information in phase difference and frequency difference, a quantizer for generating a discrete signal by making discrete the amplitude of the modulated signal generated by the quadrature angular modulator with reference to a certain level, a write head for writing the output signal of the quantizer onto the recording medium, a read head for reading information written on the recording medium, a read compensate circuit for compensating the phase and amplitude of a signal readout of the read head, and a multi-phase quadrature angular demodulator for demodulating a signal supplied from the read compensate circuit by subjecting it to multi-phase quadrature angular demodulation. By expressing information to be recorded in phase difference or frequency difference, it is made possible to record or reproduce the information at the varying timing of amplitude, and the bit inversion interval can be controlled by regulating the timing of amplitude variation.

Information recording and reproducing apparatus

An automatic equalization apparatus useful for supplying an output signal of a transversal filter simultaneously to two juxtaposed comparators, one of the two comparators performing signal identification, the other of the two comparators detecting an equalization error with the reference level changed, and extracting data from resultant two kinds of data trains by taking at least (N-1)/2+1 bits as the unit, N being the number of taps of the transversal filter, performing correlation computation, and setting tap coefficients of the transversal filter on the basis of the resultant accumulated value.

Automatic equalization method and apparatus

Non-linear intersymbol interference and noise in a received data signal are corrected through use of a Viterbi detector which estimates the most likely sequence of transmitted data symbols by keeping track of candidate data sequence that are recursively updated, based on likelihood measures which are determined by a signal processor which includes circuits for estimating hypothesized channel outputs in the absence of noise. Non-linear input-output relations are stored in one or more look-up tables which, in a preferred embodiment, are registers that store hypothesized channel output symbols in the absence of noise. The contents of the look-up tables may be modified in response to an error signal representative of the difference of the channel output signal and the look-up table output signal.

Receiver for data transmission system with nonlinearities

A tape recorder of the present invention comprises a pair of feed and take-up spools for winding a tape as recording media, a rotatable drum rotated to wind and run the tape between the pair of spools over the drum surface helically, a head for recording, reproducing or erasing signals on the tape wound over said drum surface, and control means for controlling the relative positional relationship between the head and the tape wound over the drum surface based on an error signal such that said signals are stably recorded, reproduced or erased along a desired track, the control means having means for holding the error signal during the period in which the tape is discontinued over a drum surface. The value of the error signal at the time immediately before the tape disappears from the drum surface, or the value of the error signal at the time immediately after the tape reappears over the drum surface during the preceding rotation of the drum is used as the error signal to be held, thereby allowing to stably restart the positioning control when the tape reappears over the drum surface.

Tape recorder with means for sampling and holding focusing and tracking

An adaptive transform encoder can keep a recording rate of a digital signal at a constant level. It comprises a unit for orthogonal-transforming one block of digital input signal, a unit for calculating an activity index of the orthogonal-transformed block, a unit for comparing the activity index of the block with a predetermined reference, a unit for classifying the block to a standard bit class having a predetermined number of bits when the activity index of the block is equal to the reference, classifying the block to a low bit class having a smaller number of bits than the predetermined number of bits of the standard bit class when the activity index of the block is smaller than the reference, and classifying the block to a high bit class having a larger number of bits than the predetermined number of bits of the standard bit class when the activity index is larger than the reference, a quantization unit for quantizing the input signal of the block with the number of bits designated by the bit class, a unit for selecting the block of the low bit class from the quantized blocks, an allocation unit for adding to the selected block of the low bit class the data having more bits than the number of bits of the standard bit class of the block of the quantized high bit class, and an encoder unit for encoding the quantized block signal.

Adaptive transform encoder for digital image signal in

In a system for transmitting a binary source signal from a data transmitter to a data receiver through a noisy dispersive channel, the data transmitter includes a sliding block encoder which converts the binary source signal at a given symbol rate 1/T into an encoded binary data signal at a symbol rate P/(NT), where P and N are positive integers such that N/P.ltoreq..sup.2 log(3)/2= 0.79248. Since the channel introduces intersymbol interference and noise into the encoded data signal, the data receiver is formed from the cascade of an equalizer, a sampler and a reconstruction circuit which serves to reconstruct the binary source signal at the symbol rate 1/T. The reconstruction circuit includes a detector in a cascade with a decoder having memory the equalizer, sampler and detector are arranged for the detection of a ternary data signal at the symbol rate P/(2NT).

Binary data signal transmission system

A waveform equalization method whereby a transversal filter having 5 or more tapes is included, and a difference signal output, which is obtained when an isolated impulse response waveform of a digital modulated signal is inputted to the above described filter and the output of the filter is inputted to an adder, is allowed to have intersymbol interference at .+-.T/2 with respect to the central axis time and has zero outputs at .+-.nT/2 (where n.gtoreq.2 and n is an integer).

Method and apparatus for waveform equalization

An original digital signal is converted into either a Miller-squared code signal or a Miller code signal, and undergoes serial-to-parallel conversion to produce n-phase signals (where n is desired to be a positive even number). N-phase virtual demodulated signals are simultaneously generated at clock timing having a period equivalent to 1/n times the period of the transmission clock. Out of the n-phase virtual demodulated signals, n/2 phases are selected to undergo parallel-to-serial conversion, the original digital signal being thus obtained.

Demodulation apparatus

An optical tape apparatus having improved focus and tracking control. An optical head records, reproduces, or rewrites data on an optical tape by helically scanning the tape with a laser beam. A guide plate is disposed between the optical head and the tape to prevent the beam from becoming unfocused due to fluctuation of the tape cuased by an air film between the optical head and the tape. The optical head contains a semiconductor laser and an optical system exhibiting chromatic aberration for directing the laser beam onto the tape. The optical system includes a condenser lens for focusing the beam onto the tape. Fine focus control is achieved by changing the wavelength of the laser beam by directing part of the beam reflected from the tape back to the laser, thereby changing the focal point of the beam by virtue of the chromatic aberration of the optical system. Coarse focus control is achieved by mounting the condenser lens on a piezoelectric actuator which moves the consenser lens to focus the beam onto the tape. A recording head for recording timing marks and tracking signals on the tape is disposed in advance of the optical head. A reading head reads the timing marks and the optical head reads the tracking signals. The timing marks and tracking signals are used to control the operation of the apparatus such that the tape is transported with a constant speed and data on diagonal signal tracks on the tape is accurately recorded, reproduced, or rewritten.

Optical tape apparatus with a tracking control mechanism and/or a

An apparatus for recording an reproducing a digital video signal is disclosed which includes n sampling circuits each for performing a sub-Nyquist sampling operation for the digital video signal in such a manner that the amount of data is reduced to one-n-th of an original amount (where n is a positive integer) and a pixel sampled by the sub-Nyquist sampling operation is not sampled by the remaining sampling circuits, recording/reproducing means for recording and reproducing information at all or part of pixels which are sampled by the n sampling circuits and a device for reconstructing the digital video signal from reproduced information at pixels with the aid of a synthesizing technique or interpolation technique.

Apparatus for recording/reproducing digital video signals in both a

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Inagi, Japan

Morishi Izumita