Kabushiki Kaisha Toshiba

Morio Takahashi

Hiroshi Takei

Akio Nakagawa

Ichiro Omura

Yusuke Kawaguchi

Tatsuya Yamada

Kazuo Shimokawa

Kenichi Matsushita

Noriaki Yoshikawa

Yasuhito Saito

Yoshiki Endo

Takashi Koyanagawa

Osamu Usuda

Haruki Arai

Masahiro Urase

Masako Ooishi

Taiki Miura

Tomohiro Kawano

Koichi Endo

Tsutomu Kojima

Akira Yamashita

A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

Semiconductor module

A pair of upper and lower semiconductor switching elements can switch between the conductive state and the non-conductive state when control voltages vary. A controller controls the levels of the control voltages to alternately turn on the upper and lower semiconductor switching elements. The controller controls the absolute value of the second control voltage of the lower semiconductor switching element so as to reach a mean voltage before and after the time of transition between the conductive state and the non-conductive state of the upper semiconductor switching element. The mean voltage is lower than the absolute value of a threshold voltage and higher than a reference voltage.

Semiconductor device configured to control a gate voltage between a threshold voltage and ground

A gate driver includes an edge detection circuit, an ON pulse generation circuit, first and second OFF pulse generation circuit and a status hold circuit. The first OFF pulse generation circuit generates a first OFF pulse in response to a leading or trailing edge of a control input signal, which is detected by the edge detection circuit. The status hold circuit drives an output element in response to the ON pulse outputted from the ON pulse generation circuit and holds driving status of the output element until a first OFF pulse is outputted from the first OFF pulse generation circuit. The second OFF pulse generation circuit generates a second OFF pulse in response to a protect operation signal and supplies this pulse to the status hold circuit, thereby to stop driving of the output element.

Gate driver for driving a switching element, and a power converter in which the gate driver and an output element are integrated in one-chip

Growing community of inventors

Fukaya, Japan

Morio Takahashi