Nec Electronics Corporation

Nec Corporation

Renesas Electronics Corporation

Morihisa Hirata

Hitoshi Okamoto

Masanori Tanaka

Mototsugu Okushima

Tetsuya Katou

Susumu Kobayashi

Tetsuya Akimoto

Tomohiro Kitayama

Osamu Kato

Yasuyuki Morishita

Noriyuki Kodama

Koichi Sawahata

Jun Ikeda

Toshiya Hatta

Kouji Terai

A protection circuit includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system, controls a first switch. The first switch is provided between the signal line and the first ground. The control circuit includes a capacitance element, a resistance element in series with the capacitance element, and an inverter, an output of the inverter being connected between a gate of the first switch, an input of the inverter being connected to a connecting point between the capacitance element and the resistance element.

Semiconductor device with a plurality of power supply systems

A protection circuit that includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, the second power supply system being connected to the first power supply system via a signal line through which signal transfer is performed between a circuit in the first power supply system and a circuit in the second power supply system, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system controls a switch, the switch being provided between the signal line and the first power supply.

An ESD analysis method and computer program product are disclosed. A circuit simulation is executed of design data of a semiconductor integrated circuit including a first power supply pad, a second power supply pad and a plurality of current paths between the first power supply pad and the second power supply pad, to calculate potentials in the plurality of current paths, when one of an ESD current and an ESD voltage is applied between the first power supply pad and the second power supply pad. An ESD tolerance is checked by calculating a potential difference between a first node coupled to the first power supply pad and a second node coupled to the second power supply pad, based on the calculated potentials. The first node and the second node are determined as nodes to be coupled to a border cell upon the potential difference being lower than a predetermined value.

ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device

To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET Mconnected between the pad PAD and the ground and having its gate terminal and backgate connected in common, and a potential control circuitthat controls a potential Vb of the gate terminal and the backgate of the n-type MOSFET Mbased on a potential Vin of the pad PAD. The potential control circuitcomprises n-type MOSFETs Mand M; the n-type MOSFET Mhas its gate terminal and backgate connected to backgates and drains of the n-type MOSFETs Mand M; the n-type MOSFET Mhas its source grounded and its gate terminal connected to the pad PAD via a resistance R; and the n-type MOSFET Mhas its source connected to the pad PAD and its gate terminal grounded.

Semiconductor integrated circuit device including a pad and first mosfet

An exemplary aspect of an embodiment of the present invention is a semiconductor device including a plurality of test elements formed in an array on a semiconductor substrate, an address signal generating portion that generates an address signal corresponding to each of the test elements, and a digital-to-analog converter that converts the address signal into an analog signal and outputs the converted analog signal. The present invention enables to recognize which DUT is being measured.

Semiconductor device including address signal generating protion and digital-to-analog converter

Disclosed is a semiconductor integrated circuit device that includes an output circuit with power thereof supplied from one power supply system, an input circuit with an input terminal thereof connected to an output terminal of the output circuit through a signal line and with power thereof supplied from other power supply system different from the one power supply system, and a circuit that restrains a current flowing from the output circuit into the signal line when an ESD stress is applied from the output circuit to a signal transmitting/receiving portion of the input circuit.

An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.

A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit to which electric power is supplied from second power supply wiring, and second ground wiring coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unit configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.

Semiconductor integrated device and apparatus for designing the same

A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit to which electric power is supplied from second power supply wiring, and second ground wiring coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unit configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The second interface circuit unit is placed in the vicinity of the first interface circuit unit according to a determined arrangement.

A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chipto which electric power is supplied from first power supply wiring, and first ground wiringto which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second semiconductor chipto which electric power is supplied from second power supply wiring, and second ground wiringcoupled to the second circuit unit. The first semiconductor chip includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unitconfigured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiringis coupled to the second ground wiringthrough a protection circuit, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.

System-in-package type semiconductor device

In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

MOS type semiconductor device having electrostatic discharge protection arrangement

A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unitto which electric power is supplied from first power supply wiring, and first ground wiringto which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unitto which electric power is supplied from second power supply wiring, and second ground wiringcoupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unitconfigured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.

To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.

Method and computer software product for calculating and presenting a numerical value representative of a property of a circuit

A protective circuit includes a floating gate MOSFET having a source-drain path connected between an I/O line and a source line or a ground line, a control gate connected to the I/O line and a floating gate connected to the source line or the ground line.

Growing community of inventors

Kanagawa, Japan

Morihisa Hirata