Oki Electric Industry Co., Ltd.

Tokyo Electron Limited

Renesas Technology Corp.

Morifumi Ohno

Koji Akiyama

Mitsuhiko Ogihara

Motoki Kobayashi

Shinji Ohuchi

Makoto Terui

Masaru Kadoshima

Zhang Lulu

With the objective of enabling a reduction in the size of a final semiconductor device and its thinning, and attaining facilitation of a manufacturing process, the semiconductor device includes a circuit chip having a flat mounted surface, a circuit chip smaller in size than the former circuit chip, and a sheet-like support. The latter circuit chip is formed over a substrate and has a flat back surface fixed to the substrate and a flat surface positioned on the side opposite to the back surface. The support is bonded to the surface of the latter circuit chip and supports the latter circuit chip. Then, the back surface of the latter circuit chip supported by the support is peeled from the substrate and pressed against the mounted surface, thereby fixing the back surface of the latter circuit chip and the mounted surface by an intermolecular bonding force (e.g., hydrogen bonding).

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.

A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.

A chain ferroelectric RAM includes a memory cell array having a plurality of memory cell, which connected in series between bit line and a plate line. Each memory cell includes a first ferroelectric capacitor having upper and lower electrodes between which a ferroelectric layer is provided; a second ferroelectric capacitor having upper and lower electrodes between which a ferroelectric layer is provided; and a transistor connected to the upper and lower electrodes of the first and second ferroelectric capacitors. The upper electrode of the first ferroelectric capacitor is connected to the lower electrode of the second ferroelectric capacitor, and the lower electrode of the first ferroelectric capacitor is connected to the upper electrode of the second ferroelectric capacitor in a complimentary manner.

Growing community of inventors

Tokyo, Japan

Morifumi Ohno