Intel Corporation

Other

Vlsi Technology, Inc.

Morgan J Dempsey

Jose A Maiz

Rajeev Jayavant

Matthew B Tangvald

Scott T Peiffer

A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.

Repair bits for a low voltage cache

According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Method and apparatus to adjust voltage for storage location reliability

A method and apparatus for detecting soft errors in a storage subsystem is provided. Write data generated for a write operation in a first controller is concurrently generated in a second controller and written to a storage device by the first controller. Soft errors are detected by comparing the two sets of write data by comparing respective checksums or the write data read back from the storage device by the second controller.

Fault tolerant soft error detection for storage subsystems

A method and a system for the nonlinear storage of data points of a texture map matrix within a linear memory device has two embodiments. A first embodiment involves the implementation of subdividing the texture map matrix into storage matrixes, and storing each storage matrix into distinct memory locations within the linear memory device. Each storage matrix includes at least one pair of adjacent data points from two adjacent row of data points. As a result, data points of the texture map matrix are in a nonlinear storage arrangement within the linear memory device. A second embodiment involves the implementation of subdividing the rows of the texture map matrix into multi-data point groups, and placing adjacent multi-data point groups into a linear string. The linear string is subsequently written to the linear memory device. As a result, data points of the texture map matrix are in a nonlinear storage arrangement within the linear memory device.

Method and a system for the nonlinear storage of a texture map within a

A Mini-PCI (MPCI) interface, and associated circuits and methods are provided for connecting a Peripheral Component Interconnect (PCI) device to one or more external devices. The MPCI interface, circuits and methods provide for a substantial if not full implementation of a PCI Local Bus without requiring the standard number of pins, traces, or signals. The MPCI interface includes a PCI/MPCI bridge connected between a PCI bus and to up to eight external devices in the form of MPCI devices and linear memory devices. The PCI/MPCI bridge is capable of receiving an incoming PCI transaction and multiplexing some of its signals together to create a corresponding incoming MPCI transaction. This incoming MPCI transaction may then be passed over an MPCI bus, having fewer lines and optimally operating at a higher frequency, the external devices. The process is reversed for outgoing transactions, i.e., the MPCI transactions are de-multiplexed to create PCI transactions. Additionally, the MPCI interface may also be configured to provide for direct access to linearly addressed memory devices without adding a PCI interface to the external interface. The invention may be implemented through integrated circuitry and/or computer implemented instructions, and may be included within a personal computer.

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Phoenix, AZ, United States of America

Morgan J Dempsey