Cypress Semiconductor Corporation

Other

Morgan Andrew Whately

Thinh Tran

Joseph Tzou

Cliff Zitlaw

Timothy John Williams

Harold Kutz

Jun Li

Jeffery Scott Hunt

Hans Van Antwerpen

Michael David Fliesler

Suresh Parameswaran

Muthukumar Nagarajan

Sherif Eid

David Robert Lindley

Bruce Barbara

Kenelm G Murray

Sandeep Krishnegowda

Vinod Rajan

Christopher Lee

Jithender Majjiga

A method can include, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.

Methods for error detection and correction and corresponding systems and devices for the same

A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.

Memory controller for non-interfering accesses to nonvolatile memory by different masters, and related systems and methods

A memory device can include first sense amplifiers coupled to bit lines of a memory array in a first access period and de-coupled from the bit lines in a first sense period, the first sense amplifiers configured to amplify data signals from the memory array in the first sense period; and second sense amplifiers coupled to the bit lines in a second access period that follows the first access period and configured to amplify data signals from the memory cell array in a second sense period that overlaps the first sense period.

High speed time interleaved sense amplifier circuits, methods and memory devices incorporating the same

A system and method is provided for hot de-latch of a parasitic device in an integrated circuit (IC) that restores the IC to normal operation without de-powering the IC or resulting in a loss of data. In one embodiment the method, includes reducing a voltage supplied to at least a portion of the IC from a normal operation voltage to a de-latch voltage for a time to de-latch the parasitic device without de-powering the IC. Other embodiments are also disclosed.

System and method for de-latch of an integrated circuit

Disclosed is a dynamic detector to detect an environmental condition including a power-supply level relative to a predetermined threshold signal during a training phase; and an adjustable buffer, coupled with the dynamic detector, configured to adjust output drive strength during the training phase in response to the detected environmental condition.

Method and apparatus for dynamically detecting environmental conditions and adjusting drive strength in response to the detecting

An integrated circuit (IC) including a controller integrally formed on a shared die with the IC and method of operating the same to compensate for process and environmental variations in the IC are provided. In one embodiment the IC is comprised of device and sub-circuits, and the method includes: receiving in the IC electrical power and information on at least one of one or more operational parameters of the IC; and adjusting one or more operating characteristics of at least one of the devices and sub-circuits in the IC based on the received information using a controller integrally formed on a shared die with the IC. Other embodiments are also disclosed.

System and method to compensate for process and environmental variations in semiconductor devices

An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

Circuits and methods for programming integrated circuit input and output impedances

Disclosed is an accumulation memory circuit for providing a fast read, modify, and write operation in a single clock cycle time. The memory circuit is configured to read data stored in the memory device at an address. The memory circuit includes a reconfigurable adder unit generating read, accumulate and write output in a single clock cycle. The memory circuit is further configured to minimize data overflow. A high speed accumulation method comprises resetting a memory circuit; reading from an address of the memory circuit; performing internal addition within the memory circuit and rewriting into the address of the memory circuit in a single clock cycle.

Area efficient and fast static random access memory circuit and method

In one embodiment, an integrated circuit device includes a power on reset (POR) circuit and a stochastic reset circuit configured to control enabling and disabling of the POR circuit. The stochastic reset circuit may have a value from among many possible values. The POR circuit may be enabled during a power up sequence of the device when the value of the stochastic reset during the power up is not a value designated to allow disabling of the POR circuit. The stochastic reset circuit may be configured such that the probability of the POR circuit being disabled during the power up is extremely low. After the power up sequence, the stochastic reset circuit may be controlled to allow disabling of the POR circuit to conserve power.

Stochastic reset circuit

A memory device can include a group of memory cells, which can be arranged in a column () that receives power by way of a first cell supply nodes (-to-). A current limiter () can be situated between first cell supply nodes (-to-) and a power supply (VH), and limit a current (llimit) to less than a latch-up holding current (lhold_lu) for the group of memory cells (). In a particle event, such as an &#x3b1;-particle strike, a current limiter () can prevent a latch-up holding current (lhold_lu) from developing, thus preventing latch-up from occurring. Current limiter () can include p-channel transistors and/or resistors, and thus consume a relatively small area of the memory device.

Memory array with current limiting device for preventing particle induced latch-up

A method and apparatus comprising a first circuit configured to generate a first output in response to a first input, a second circuit configured to present a second output in response to a second input, and a third circuit configured to generate a first voltage signal and a second voltage signal in response to the first output and said second output. The first voltage signal may be above the positive supply and the second voltage signal may be below the negative supply.

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San Francisco, CA, United States of America

Morgan Andrew Whately