Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Mordekhay Zehavi

Mahmud Asfur

Yonatan Tzafrir

Israel Zimmerman

Eyal Widder

Yuri Ryabinin

Or Faerman

Yossef Tamir

Rustam Freidel

Various devices, such as storage devices or systems are configured to transmit data between various components over one or more interfaces. The operation of these interfaces is based on the mechanical limits of the components doing the communication, often latches. Latches often require a setup and hold time limit on the signal being transmitted to be held a desired value. Because the physical effects of the environment, such as voltage being provided, temperature of the component, for example, can affect the operation of the latch, there is often a large margin used to operate them. These large margins avoid errors but decrease overall speed of the interface. By utilizing a test latch within an interface bus group with a drop in operating voltage, changes in output detected can be indicative of upcoming errors. Once detected, the error can be remedied by increasing voltage, lowering operating speeds, or cooling the components.

Interface bus speed optimization

Various apparatuses, systems, methods, and media are disclosed to provide wired communication interface with common mode voltage adjustment for high bit rate communication between devices. In one example, a high speed data communication interface can split the input signal into a high frequency component and a low frequency component. The high speed data communication interface can adjust the common mode voltage using the low frequency component and combine the high frequency component and the low frequency component by superposition after adjusting the common mode voltage.

High bit rate communication interface with common mode voltage adjustment

A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.

High throughput, low power, high parity architecture for database SSD

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.

Dynamic calibration of frequency and power storage interface

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

Method for maximizing frequency while checking data integrity on a physical interface bus

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.

Method for maximizing power efficiency in memory interface block

A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.

Systems and methods of adjusting an interface bus speed

A storage device may be configured to adjust a frequency of a clock signal. The clock signal may be associated with a data transfer rate of data to be communicated between a controller and a memory of the storage device. In some implementations, the frequency maybe adjusted responsive to at least one of a supply voltage provided to the storage device, a temperature of the storage device, or a physical characteristic of the storage device.

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Raanana, Israel

Mordekhay Zehavi