Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundires Inc.

Moosung M Chae

Xunyuan Zhang

Larry Zhao

Hui Zang

Jinping Liu

Jiehui Shu

Errol Todd Ryan

Nicholas V Licausi

Sean Xuan Lin

Ming He

Christian Witt

Kunaljeet Tanwar

Xiaoqiang Zhang

Ki Young Lee

Ailian Zhao

Haizhou Yin

Joseph Francis Shepard, Jr

Zhiguo Sun

Huy Cao

Songkram Srivathanakul

Woo Sik Kim

Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

Electrical fuse formation during a multiple patterning process

Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, such that the doped metal layer overlies the conductive region, the doped metal layer including a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material, the interface liner formed only on sidewalls of the contact opening and in direct contact with the ILD material and only at an interface of the doped metal layer and the ILD material.

IC structure with interface liner and methods of forming same

Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: providing a structure with: a conductive region, and an inter-level dielectric (ILD) material positioned on the conductive region, wherein the ILD material includes a contact opening to the conductive region; forming a doped metal layer within the contact opening such that the doped metal layer overlies the conductive region, wherein the doped metal layer includes a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material.

The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

Airgaps to isolate metallization features

A method of forming a self-forming barrier includes selectively removing a portion of a semiconductor dielectric layer to form a three-dimensional pattern within a remaining portion of the dielectric layer. A metal liner layer is disposed on a surface of the pattern to provide a metal lined pattern. A metal filling is disposed over the metal lined pattern, the metal filling being at least partially composed of a metal used in the metal liner layer. Diffusion ions are disposed in one of the metal filling and the metal liner layer. Heat is applied to the metal filling and metal liner layer to diffuse the diffusion ions from one of the metal filling and the metal liner layer into the dielectric layer to form a barrier layer between the metal liner layer and the dielectric layer.

Methods of self-forming barrier formation in metal interconnection applications

A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal.

Electro-migration enhancing method for self-forming barrier process in copper mettalization

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal capping layer on first sidewalls of a copper line while leaving exposed portions of a dielectric layer that are laterally adjacent to the copper line exposed. An ILD layer is deposited overlying the metal capping layer and the exposed portions of the dielectric layer.

Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same

Integrated circuits with single core inductors and methods for producing them are provided. Embodiments include forming a trench in a dielectric layer; forming a first metal-oxide hard mask by disposing a metal hard mask and an oxide hard mask over the dielectric layer and in strips in the trench; forming metal line trenches through the first metal-oxide hard mask and into the first dielectric layer on opposite sides of the inductor trench and first vias; filling the first metal line trenches, first vias, and trench; forming another dielectric layer and a second metal-oxide hard mask over the filled trench; forming a second trench through the second metal-oxide hard mask and into the second dielectric layer and second metal line trenches and second vias; and filling the second metal line trenches, second vias, and second trench.

Semiconductor device having non-magnetic single core inductor and method of producing the same

Electro-migration enhancing method for self-forming barrier process in copper metalization

A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.

Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same

A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Methods for integration of pore stuffing material

A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

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Englewood Cliffs, NJ, United States of America

Moosung M Chae