Samsung Electronics Co., Ltd.

Samsung Electronics Ltd.

Moongyung Kim

Youngsik Eom

Donghyeon Ham

Euiyeon Won

Ara Cho

An electronic device including a main memory, a plurality of caches that are hierarchically connected, the plurality of caches configured to store part of data stored in the main memory, and processing circuitry configured to transmit a memory request for desired data to the plurality of caches and the main memory, the memory request including cache allocation range information associated with the desired data, and each of the plurality of caches are configured to, determine whether to perform an operation corresponding to the memory request based on the cache allocation range information.

Electronic device allocating data in plurality of caches using cache allocation range information

The present disclosure relates to an electronic device, a memory device, and an operating method of the memory device. An example memory device includes a first bank, a second bank, and a cache controller. The cache controller is configured to set a hash function based on a power control signal that comprises instructions to stop supplying power to the first bank, and to map the first address and the second bank based on the hash function and a first transaction provided by a master after the power control signal is input.

Electronic devices, including memory devices, and operating methods thereof

Disclosed are system-on-chip devices (SoCs) and operating methods thereof. A system-on-chip (SOC) may include a memory including a history storage, a processor configured to execute an application, performance optimization module configured to generate and transmit optimized control information for the processor executing a function included in the application, based on a history corresponding to the function, when the processor executes the function and the history corresponding to the function is in the history storage, and a performance management module configured to generate a control signal for controlling performance of the processor, based on the optimized control information received from the performance optimization module, wherein the history includes control information for the processor and utilization information accumulated according to the control information, the control information having been accumulated during at least one time of previous execution of the function.

System on chip and operating method thereof

A system on chip is provided. The system on chip includes: a plurality of memory controllers respectively connected to a plurality of memory devices; a plurality of logic circuits, each logic circuit being configured to perform a data processing operation using at least one of the plurality of memory controllers; and a bus connection interface configured to select a first hash function from among a plurality of hash functions based on a first address region corresponding to first addresses received from a first logic circuit from among the plurality of logic circuits, obtain hashed first addresses by applying the first hash function to the first addresses, and connect at least one of the plurality of memory controllers to the first logic circuit using a first access method that corresponds to the hashed first addresses.

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Suwon-si, South Korea

Moongyung Kim