Samsung Electronics Co., Ltd.

MoonChul Choi

Jaehyeok Baek

SungYong Cho

Hye-Ran Kim

Donggun An

Min Ho Maeing

Seongyeal Yang

Provided is a memory system including: a memory device; and a memory controller configured to transmit a command and address (CA) signal and a data clock (WCK) signal to the memory device, and transmitting a data (DQ) signal to the memory device or receive the DQ signal from the memory device. The memory device may include a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal, a CA sampler configured to sample the CA signal based on the first division clock signal, and a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and the memory controller may include processing circuitry configured to enter CA training in response to receiving the parity error signal.

Memory device, memory system and method for operating memory system including command and address training

A ZQ calibration circuit included in a semiconductor memory device includes a reference voltage selector configured to output a reference voltage selected from among a first reference voltage and a second reference voltage generated based on a first supply voltage and a second supply voltage, in response to a selection signal, a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage, and a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is toggled. Levels of the first and second reference voltages are different from each other, smaller than a level of the first supply voltage, and greater than a level of the second supply voltage.

ZQ calibration circuit, operation method of the ZQ calibration circuit, and semiconductor memory device

Provided is a transmitting device for enlarging the size of a data eye of a transmission signal. The transmitting device includes an output driver including a plurality of driver circuits that drive a plurality of multi-level signals onto an output node, and a logic circuit configured to detect a direction of a pull-up or pull-down operation of each of the plurality of driver circuits by transitions of the plurality of driver control signals and generate pulse signals. The plurality of multi-level signals are driven based on a plurality of driver control signals and pulse signals, respectively, and the logic circuit provides a pulse signal to at least one static driver circuit connected to a driver control signal that does not transition, from among the plurality of driver circuits.

Growing community of inventors

Suwon-si, South Korea

MoonChul Choi