Advanced Micro Devices Corporation

Moon-Yee Wang

Patrick T Chuang

Robert L Yau

Hiroshi Yoshida

James Jiahua Yu

Hong-Gee Fang

Robin W Cheung

A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.

Content addressable memory array with priority encoder

A content addressable memory array includes an array of M words containing bits configured in N bits for each word. One of the bits in each of the words is a settable skip bit, and during a search of the memory array, the array is examined to detect the presence therein of skip bits. If a skip bit is detected in any one of the words, that word containing the detected skip bit is eliminated from the search. Each word in the array also contains an empty bit which is used to indicate an empty word location in the array. When all empty bits are set, the array is automatically reset to empty or zero.

Content addressable memory array with maskable and resettable bits

A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.

Content addressable memory array system with multiplexed status and

A memory comprising apparatus for selecting redundant rows of memory cells wherein the addressing of a defective regular row of memory cells coupled to a first set of bit lines results in the selection of a redundant row of memory cells coupled to a second set of bit lines such that signal interference resulting from the simultaneous enablement of two word lines in the memory is avoided.

Switching plane redundancy

The substrate active region contains the source and drain regions for the transistors in each cell. The grounded drains of the two pulldown transistors extend symmetrically into the three adjacent cells coupling with six other pulldown drains. This common ground node has a single upward contact to the metal ground lead. The poly-2 has a similar voltage node coupling eight pulldown resistors in four adjacent cells to the metal Vdd lead. The poly-2 forming the lightly doped resistor area has a heavily doped conductive area at each end for coupling the resistor into the pulldown circuit. The pulldown gate bands have 45 degree bends to maximize the gate area relative to the pass gate area. The gate bends cooperate with corresponding 45 degree slants in the edges of the active region to minimize the effect of misalignment. A conductive poly word line forms the pass gates just above the active region. A metal word line connects periodically with the poly word line to minimize the effect of the distributive resistance of poly. Poly-2 is used to build up the contact from the drains of the pass transistor in the substrate active region to the metal bit leads. The lateral spread of the contact aperture is limited leaving a marging of insulating oxide between the bit contact and the pass gate structure.

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Cupertino, CA, United States of America

Moon-Yee Wang