Hynix Semiconductor Inc.

Skhynix Inc.

Moon-Sig Joo

Kwon Hong

Ki-Hong Lee

Won-Joon Choi

Heung-Jae Cho

Yong-Soo Kim

Sung-Jin Whang

Bo-Min Seo

Kyoung-Eun Chang

Se-Aug Jang

Yun-Hyuck Ji

Sun-Hwan Hwang

Won-Kyu Kim

Hyung-Chul Kim

Jung-Yeon Lim

Young-Wook Lee

Beom-Yong Kim

Seung-Woo Shin

Seung-Mi Lee

Woo-Young Park

Seung-Ryong Lee

Yong-Seok Eun

Sung-Hoon Lee

Jung-Nam Kim

Ji-Won Moon

Jun-Yeol Cho

A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region.

Method and gate structure for threshold voltage modulation in transistors

A method for fabricating a semiconductor device includes: forming a gate dielectric layer over a substrate; forming an etch stop layer over the gate dielectric layer; forming a first work function layer that covers a first portion of the etch stop layer and a sacrificial compound that covers a second portion of the etch stop layer; exposing the second portion of the etch stop layer by removing the sacrificial compound; and forming a second work function layer over the second portion of the etch stop layer and the first work function layer.

Semiconductor device and method for fabricating the same

A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.

A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.

Method for fabricating semiconductor device

A semiconductor device includes: a vertical electrode provided over a substrate; a variable resistance layer provided at least a sidewall of the vertical electrode; a plurality of horizontal electrodes extending from the sidewall of the vertical electrode and having the variable resistance layer interposed; a transition metal oxide layer provided (i) between the vertical electrode and the variable resistance layer or (ii) between the plurality of horizontal electrodes and the variable resistance layer; and a threshold voltage switching layer provided in the transition metal oxide layer and selectively between the vertical electrode and the any of the plurality of horizontal electrodes.

Semiconductor device and electronic device including the same

A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.

Non-volatile memory device and method for fabricating the same

A resistance variable memory device includes: a first electrode; a second electrode; a resistance variable layer interposed between the first electrode and the second electrode; and nano particles that are disposed in the resistance variable layer and have a lower dielectric constant than the resistance variable layer.

Resistance variable memory device including nano particles and method for fabricating the same

A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

Method for fabricating vertical channel type nonvolatile memory device

A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction.

3D nonvolatile memory device and method for fabricating the same

A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.

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Gyeonggi-do, South Korea

Moon-Sig Joo