Samsung Display Co., Ltd.

Silicon Image Gmbh

Moon-Sang Hwang

Deog-Kyoon Jeong

Won-Jun Choe

Han-Kyu Chi

Bong-Joon Lee

Sang-Hyun Lee

Sang-Soo Kim

Jun-Sang Park

Seung-hoon Lee

Dong-Yong Shin

Sang-Kuk Kim

Jong-Sang Choi

Weon-Jun Choe

Sang-Jun Cho

Won-Kang Kim

Tai-Ji An

Hyung-Rok Lee

Hyun-Chang Kim

A digital-to-analog converter may include a converting unit and a distributing unit. The converting unit may generate a first analog signal set based on less-than-all bits of an image data set in a first period and may generate a second analog signal set based on all bits of the image data set in a second period. The all bits may include at least 2 bits. The distributing unit may include output terminals, may distribute the first analog signal set to the output terminals in a first sequence in the first period, and may distribute the second analog signal to the output terminals in a second sequence. The second sequence may be opposite to the first sequence.

Digital-to-analog converter, driving integrated circuit, and display device

A display device is provided. The display device includes: a timing controller and a data driver. The timing controller is configured to receive input data, a main clock signal, a synchronization signal, or a protocol signal, to generate an internal clock signal by using the main clock signal, to convert the input data into image data, and to transmit the synchronization signal or the protocol signal using the internal clock signal. The data driver is configured to recover the synchronization signal or the protocol signal from the internal clock signal, and to drive the image data by using the recovered synchronization signal or the protocol signal.

Display device for high-speed data transmission and method of driving the same

A data driver capable of generating pre-emphasis voltages is provided. The data driver includes a pre-emphasis unit for comparing previous input data signals with current input data signals to generate pre-emphasis data signals, a first register unit for storing the current input data signals from the pre-emphasis unit and for supplying the previous input data signals to the pre-emphasis unit, and a second register unit for storing the pre-emphasis data signals.

Data driver and method of driving the same

A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.

Coarse lock detector

A display device is disclosed. According to some aspects, the display device includes a display panel for displaying an image, data drivers for supplying data signals to the display panel such that the display panel displays an image, and a timing controller for setting the data drivers and 3n (where n is a natural number) ports. The display device is configured to transmit an R transmission signal including R data bits, a G transmission signal including G data bits, and a B transmission signal including B data bits to the data drivers through the 3n ports. According to some aspects, a display device capable of securing a band width required for driving a three dimensional image without unnecessarily increasing ports and without increasing the transmission speed of the ports and a method of driving the same are disclosed.

Display device and method of driving the same

A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.

Level-down shifter

A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.

Coarse lock detector and delay-locked loop including the same

A method and apparatus for 2&#xd7; oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 &#x3bc;m CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10.

Data sampling method and apparatus with alternating edge sampling phase detection for loop characteristic stabilization

A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.

Phase lock loop with coarse control loop having frequency lock detector and device including same

In a class of embodiments, an adaptive equalization circuit that implements a joint adaptation algorithm. Other embodiments are receivers that include such an adaptive equalization circuit, and joint adaptation equalization methods. The equalization circuit includes a filter having a low-frequency-gain path (sometimes referred to as a low-frequency filter) and a high-frequency-boosting path (sometimes referred to as a high-frequency filter). The high-frequency filter typically includes a high-pass filter in series with an amplifier having adjustable gain. A high-frequency-boosting tuning loop controls the adjustable gain applied by the high-frequency filter. A low-frequency-gain tuning loop controls the adjustable gain applied by the low-frequency filter.

Growing community of inventors

Yongin, South Korea

Moon-Sang Hwang