Samsung Electronics Co., Ltd.

Moon-Kyung Kim

Yu-sin Yang

Sang-Mun Chon

Chung-Sam Jun

Sun-Yong Choi

Joung-Soo Kim

Sandip Tiwari

Chung-sam Jun

Chung-woo Kim

Dong-Wook Seo

Da-Som Lee

Choong-Man Lee

Yoon-dong Park

Yun-Jung Jee

Tae-Min Eom

Soo-Doo Chae

Yu-Sin Yang

Myeong-Jin Oh

Ravishankar Sundararaman

Seong-Hun Moon

Jo-Won Lee

Se-Yeong Lee

Joshua Mark Rubin

An electronic device is provided. The electronic device includes a housing, a touchscreen display, a wireless communication circuit, a processor electrically connected to the touchscreen display and the wireless communication circuit, and a memory electrically connected to the processor, wherein the memory is configured to store an application program comprising a user interface, and store an instruction that, when executed, enables the processor to store a permission for accessing, by an application program stored in the memory, at least one among hardware components or software components of the electronic device, activate the application program, allow the application program to access the at least one among hardware components or software components based on the stored permission and display a user interface (UI) of the application program on the touchscreen display, hide a part of the user interface while the application program is executed in a background state, and monitor whether the application program uses the at least one among hardware components or software components while the application program is executed in the background state.

Method and electronic device for controlling permission of application program

An electro-mechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.

Electro-mechanical transistor

A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.

CMOS thin film transistor comprising common gate, logic device comprising the CMOS thin film transistor, and method of manufacturing the CMOS thin film transistor

A defect inspecting apparatus includes a first support unit supporting a standard sample having standard defects, a second support unit supporting a wafer having target defects, a light source irradiating an incident light to the standard sample or the wafer, a light receiving part collecting reflection light reflected from the standard sample and the wafer, a detection part detecting the standard defects and the target defects by using the reflection light, a comparing part comparing information obtained using the reflection light reflected from the standard sample with a predetermined standard information of the standard defects to confirm a reliability of a step for detecting the target defects and a determination portion determining whether the step is allowed to be performed or not.

Method and apparatus for inspecting target defects on a wafer

In a method and an apparatus for inspecting a wafer surface, a wafer is loaded into a chamber. An incident light including a first light for sensing a vertical position of the wafer and a second light for inspecting the wafer surface is irradiated onto the wafer. The first light is reflected on an inspection region or a next inspection region of the wafer and is detected to control a wafer position. The second light is scattered on the inspection region and is detected to inspect the wafer surface of the inspection region. Position information of a wafer is examined and a position of the wafer is adjusted before inspecting a surface of inspection region of a wafer so as to enable accurate inspection of the wafer surface.

Method and apparatus for inspecting a wafer surface

In a method for inspecting a defect in accordance with one aspect of the present invention, an object is divided into a plurality of regions. Reflectivity of each of the plurality of regions is obtained. Amplification ratio for each region is determined using the reflectivity. A light is irradiated onto the regions. A light reflected from a first region is amplified by a first amplification ratio that is determined for the first region. Moving the irradiated light from the first region to a second region is detected. A light reflected from the second region is amplified by a second amplification ratio that is determined for the second region. The amplified lights from the first region and the second region are analyzed to determine an existence of a defect on the object.

Method and apparatus for inspecting defects

Growing community of inventors

Gyeonggi-do, South Korea

Moon-Kyung Kim