Samsung Electronics Co., Ltd.

Moon-kyung Kim

Jo-won Lee

Chung-woo Kim

Byong-man Kim

Soo-doo Chae

Hee-soon Chae

Won-il Ryu

Jung-hyun Lee

Eun-hong Lee

Hyun-sang Hwang

Seok-yeol Yoon

Hyung-lae Roh

A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same

A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (SiN); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.

Nonvolatile semiconductor memory device having a gate stack and method of manufacturing the same

In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.

Silicon-oxide-nitride-oxide-silicon (SONOS) memory device and methods of manufacturing and operating the same

A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.

SONOS memory device

In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation of the gate lamination pattern includes sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, forming an upper layer including a plurality of quantum dots on the single electron storage medium, forming a gate electrode layer on the upper layer to be in contact with the plurality of quantum dots, and patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.

Method for manufacturing a single electron memory device having quantum dots between gate electrode and single electron storage element

A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.

Single electron memory device comprising quantum dots between gate electrode and single electron storage element and method for manufacturing the same

A multi-value single electron memory using a multi-quantum dot, in which the floating gates (FG) of a EEPROM or a flash memory are formed to act as two quantum dots, and the two quantum dots are applied to multi-value memories, and a driving method of the multi-value single electron memory, are provided. Thus, a multi-value memory can be realized using two quantum dots. Also, an ultra-highly integrated memory of 1 Tb or greater can be realized without encountering a physical limit such as a short channel effect (SCE) caused by scaling down MOSFETs, in contrast to other memories.

Multi-value single electron memory using double-quantum dot and driving method thereof

A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO ) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.

Single electron transistor using porous silicon and manufacturing method thereof

Single electron transistor using porous silicon

A metal nitride oxide semiconductor (MNOS) type memory using a threshold voltage variation (&Dgr;Vth) due to charging of a single electron when the width of a channel of the memory is set to be smaller than or equal to the Debye screen length (LD) of an electron, and a driving method thereof, are provided. The MNOS memory uses a threshold voltage variation (&Dgr;Vth) due to charging of a single electron occurring when the width of a channel is set to be smaller than or equal to the Debye screen length (LD) which depends on the impurity concentration of a semiconductor substrate.

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Yongin-si, South Korea

Moon-kyung Kim