Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Labgenomics Co., Ltd.

Moon Il Kim

Young Gwan Ko

Myung Sam Kang

Yun Tae Lee

Bong Ju Cho

Han Bit Kim

Byoung Hwa Lee

Yong Jong Park

Jun Young Kim

Yong Ho Baek

Young Sik Hur

Jeong Ho Lee

Doo Hwan Lee

Sang Min Lee

Sang Kyu Lee

Sang-Joon Hwang

Dae Hyun Park

Tae Hee Han

Mi Ja Han

Seong Hee Choi

Yong Koon Lee

Young Chan Ko

Byoung Chan Kim

Hyun Gyu Park

Yong Soon Jang

Yong Jin Park

Dae-Yeon Cho

Min-Ah Woo

Mi Jin Choi

Yeon Seop Yu

A method includes forming a first package structure including a first connection member including a first redistribution layer, a first frame having a first through-portion, a first semiconductor chip having a connection pad electrically connected to the first redistribution layer, and a first encapsulant covering a portion of each of the first frame and the first semiconductor chip, forming a second package structure including a second connection member including a second redistribution layer, a second semiconductor chip having a second connection pad, and a second encapsulant covering a portion of the second semiconductor chip, forming a first through-via, the first through-via electrically connecting to the second redistribution layer, and laminating the first package structure on the second package structure. After the laminating, the first through-via penetrates through the first frame, the first encapsulant, and a portion of the first connection member, and is electrically connected to the first redistribution layer.

Semiconductor package

A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.

Semiconductor package including frame in which semiconductor chip is embedded

A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.

A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.

Semiconductor package and antenna module including the same

A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other.

A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.

An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component.

Electronic component package

A fan-out semiconductor package includes first and second structures. The first structure includes a first semiconductor chip, a first encapsulant, and a connection member. The second structure includes a second semiconductor chip, a second encapsulant, and conductive bumps. The first and second structures are disposed so that active surfaces of the first and second semiconductor chips face each other. The conductive bumps are electrically connected to a redistribution layer, and connection pads of the first and second semiconductor chips are connected to each other through the redistribution layer in a signal manner. Signal transmission times between one point of the redistribution layer and connection pads of each of the first and second semiconductor chips are substantially the same as each other.

Fan-out semiconductor package

A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole of the first connection member, the semiconductor chip including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a passive component attached to the active surface of the semiconductor chip, an encapsulant encapsulating at least a portion of the first connection member and the inactive surface of the semiconductor chip, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, the first connection member and the second connection member each including at least one redistribution layer electrically connected to the connection pads of the semiconductor chip, and the passive component being electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the first connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip.

Disclosed herein are an electronic component and a method of manufacturing the same. In an electronic component having a conductor formed in an insulator and providing an external electrode electrically connected to the conductor on an outer surface of the insulator, a curvature of the external electrode in a via machining region is decreased at a predetermined level or less, thereby making it possible to decrease defect generation due to a glare-reflection of a laser.

Electronic component and method of manufacturing the same

An electronic component embedded printed circuit board includes a core having a cavity; an electronic component inserted in the cavity; insulating layers laminated on top and bottom of the core and mixed with a coupling agent, which has functional groups respectively acting on an organic material and an inorganic material, to be bonded to an outer peripheral surface of the electronic component; and circuit patterns provided on the insulating layers.

Electronic component embedded printed circuit board

A package substrate includes an insulating layer; and circuit patterns formed on the insulating layer and divided into pad areas and pattern areas that have different heights. In one aspect, there can be a non-conductive paste (NCP) interposed between the circuit patterns and pads of a die connected to the circuit patterns to fix the die onto the insulating layer.

Growing community of inventors

Suwon-si, South Korea

Moon Il Kim