Samsung Electronics Co., Ltd.

Moon-Hyun Yoo

Dong-hyun Kim

Soo-Han Choi

Chul-Hong Park

Yoo-Hyon Kim

Jae-pil Shin

Jong-Bae Lee

Joon-Ho Choi

Jin Hwan Choi

Sang-ho Park

Jae-Seok Yang

Jeong-Lim Nam

Yoonna Oh

Hye-Soo Shin

Jong-bae Lee

Kwang-jai Yoo

Kyo-sun Kim

Jeong-min Choi

Young-Chan Ban

Young-Ile Kim

Jeong-Taek Kong

Jae-Pil Shin

Jeong-Yeol Kim

Seuk-Whan Lee

In a method of inspecting a mask, an image of a pattern on the mask may be obtained. A histogram of the image by grey levels may be obtained. The histogram may be compared with information of the pattern to detect a defect of the mask. Thus, reliability of defect detection in the mask may be remarkably improved.

Method of inspecting a mask

In a method of designing a mask layout, a wiring region for forming a metal wire is established, the wiring region having at least a standard width. Contact regions for forming contacts electrically connected to the metal wire are established in the wiring region. The contact regions adjacent to each other are grouped to divide the wiring region into a first region and a second region including the contact regions. First dummy regions are established in the first region, the first dummy regions corresponding to regions for forming first dummy patterns. Second dummy regions are established among the contact regions in the second region, the second dummy regions corresponding to regions for forming second dummy patterns.

Method of designing a mask layout

A method for simulating an integrated circuit includes performing a power supply voltage tuning operation to find a power supply voltage at which a simulation of the integrated circuit at an operating frequency passes a functional requirement, identifying a weak signal node based on the simulation result, and performing a size tuning operation on the weak signal node of the integrated circuit.

Event driven switch level simulation method and simulator

A method of creating a layout of a set of masks including an alternating phase shifting mask (APSM) and a halftone phase shifting trim mask (HPSTM) is provided. The APSM includes first and second phase shifting areas and a first opaque pattern. The first and second phase shifting areas are disposed adjacent to each other and have different phases for generating destructive interference. Further, the first and second phase shifting areas define an access interconnection line. The first opaque pattern is formed on a transparent substrate to define the first and second phase shifting areas. The HPSTM includes a second opaque pattern on the transparent substrate and a halftone pattern. The second opaque pattern prevents an access interconnection line from being erased. The halftone pattern defines a pass interconnection line connected to the access interconnection line.

Method of creating a layout of a set of masks

Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects. The first and second schematics are then combined at corresponding first and second ports within the first and second schematics, respectively. Operations also include generating an integrated circuit netlist by generating a circuit schematic that defines post-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the post-layout interconnects. This circuit schematic is then combined with the first schematic at corresponding first and second ports therein. These embodiments may also be configured to generate a layout schematic from the first schematic of the integrated circuit and generate parasitic resistances and capacitances of the post-layout interconnects that extend between a plurality of cells in the layout schematic. Operations are then performed to generate parasitic resistances and capacitances of interconnects internal to at least one cell in the layout schematic.

Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages

Functional and temporal aggressor classification methods that provide increased efficiency and accuracy for classifying aggressor signal lines of an integrated circuit for purposes of analyzing crosstalk of the circuit. In one aspect, an aggressor classification method for analyzing crosstalk of a circuit comprises (a) obtaining CNF (conjunction normal form) clauses of signal lines from a victim to a predetermined signal line and from an aggressor to a predetermined signal line for circuit analysis using a backward search, and obtaining CNF clauses of the victim and the aggressor, and summing up the CNF clauses of the victim and the aggressor to obtain a final CNF clause, (b) obtaining CNF clauses with respect to various cases in which logic values of the victims and aggressors are varied in the final CNF clause, and (c) analyzing the CNF clauses obtained in step (b) to classify aggressors as true or false aggressors, wherein an aggressor is classified as a true aggressor if a result of a given CNF clause has a vector, and classifying an aggressor as a false aggressor if a result of a given CNF clause has no vector.

Aggressor classification method for analyzing crosstalk of circuit

A phase edge phase shift mask and a fabrication method thereof for enforcing a width of a field gate image located on a field region, which is weakened by a two exposure process, by using a phase shift mask and a trim mask on a semiconductor substrate, and enforcing a width of the field gate image to maximize a current driving capability of the semiconductor device.

Phase edge phase shift mask enforcing a width of a field gate image and fabrication method thereof

A set of masks including an alternating phase shifting mask (APSM) and a halftone phase shifting trim mask (HPSTM) is provided. The APSM includes first and second phase shifting areas and a first opaque pattern. The first and second phase shifting areas are disposed adjacent to each other and have different phases for generating destructive interference. Further, the first and second phase shifting areas define an access interconnection line. The first opaque pattern is formed on a transparent substrate to define the first and second phase shifting areas. The HPSTM includes a second opaque pattern on the transparent substrate and a halftone pattern. The second opaque pattern prevents an access interconnection line from being erased. The halftone pattern defines a pass interconnection line connected to the access interconnection line.

Mask for manufacturing a highly-integrated circuit device

Dummy patterns are generated for a region of an integrated circuit that is divided into buckets by obtaining a local pattern density for a respective bucket and adjusting a density of the dummy pattern for the respective bucket as a continuously variable function of the respective local pattern density and a target density for the region. By providing a continuously variable dummy pattern density, the desired density of the dummy pattern group may be adjusted precisely, to thereby reduce or eliminate loading effects. The density of the dummy pattern for the respective bucket may be calculated according to a formula in which the density of the dummy pattern is continuously variable. The dummy patterns may include features of fixed pitch and a size of the features of fixed pitch is increased or decreased as a continuously variable function of the respective local pattern density and the target density for the region.

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Kyungki-do, South Korea

Moon-Hyun Yoo