Samsung Electronics Co., Ltd.

Moon-Han Park

Jae-Yoon Yoo

Soo-Jin Hong

Han-Sin Lee

Ho Young Lee

Seung-Hwan Lee

Seok-Jun Won

Hwa-Sung Rhee

Yong-Kuk Jeong

Dong-Ho Ahn

Tai-Su Park

Hong-Ki Kim

Yu-gyun Shin

Dae-jin Kwon

Jin-Hwa Heo

Tai-su Park

Eun-Kee Hong

Ho-kyu Kang

Hong-Gun Kim

Ju-Seon Goo

Ho-Kyu Kang

Byou-ree Lim

Myong-geun Yoon

Kyung-Hun Kim

A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.

Capacitor for a semiconductor device and method of fabricating same

A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device

Methods of preparing improved semiconductor substrates having gate oxide layers formed thereon, and use of such substrates in fabricating improved semiconductor devices, are disclosed. The methods include a first step of performing a cleaning process for removing a natural oxide layer formed on a semiconductor substrate and also for removing an oxide layer generated by the removal of the natural oxide layer; a second step of executing a hydrogen annealing process to form a hydrogen passivation layer and for further reducing a surface roughness of the semiconductor substrate completed in the cleaning process; a third step of forming a gate oxide layer thereon; a fourth step of performing a nitridation process on the gate oxide layer to prevent the semiconductor substrate from a permeation of ions during a subsequent gate electrode formation step; and, a fifth step of performing a subsequent thermal process to stabilize a surface of the gate oxide layer, thereby improving a defect rate of the device caused in forming the gate oxide layer.

Method of forming gate oxide layer in semiconductor devices

In a trench isolation method, an etching mask pattern for forming a trench is formed on a semiconductor substrate. The substrate is etched to form a trench. An insulating layer is formed to fill the trench, and then a material layer is formed on the insulating layer. In this case, the material layer is made of material formed at a high temperature to density the insulating layer. The material layer and the insulating layer are planarly etched and the etching mask pattern is removed, so that a trench isolation layer is completed. Accordingly, although a densification process is avoided, it is possible to form a device isolation layer having a favorable surface profile.

Trench isolation method

In a method of fabricating a non-volatile memory device with a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a silicon nitride layer, which is a charge trapping layer, and a polysilicon layer, which is a control gate electrode, are electrically isolated from one another in the resulting structure. According to the method, a silicon oxide layer as a tunneling layer and a silicon nitride layer pattern as a charge trapping layer are formed on a semiconductor substrate; an oxidation process is performed to form a silicon nitride oxide layer, as a blocking layer, at top and sides of the silicon nitride layer pattern and to form a gate insulating layer at an exposed portion of the semiconductor substrate; and a control gate electrode is formed on the silicon nitride oxide layer and the gate insulating layer.

Method of fabricating non-volatile memory device having a structure of silicon-oxide-nitride-oxide-silicon

A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.

Method for forming trench type isolation film using annealing

A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane (&lsqb;SiH NH&rsqb;n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 &angst; from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.

Method of forming an insulating layer in a trench isolation type semiconductor device

A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Method of forming shallow trench isolation layer in semiconductor device

A method for forming a trench isolation in a semiconductor device is provided in which a first heat treatment process is conducted on a thermal oxide layer previously formed in a trench at temperature range from about 1000.degree. C. to 1200.degree. C. for about 1 to 8 hours so as to remove defects in a semiconductor substrate and oxygen impurities within the semiconductor substrate resulting from a step of forming the trench in the semiconductor substrate. As a result, a subsequent second heat treatment process for densifying a trench filling material such as a CVD oxide layer can be performed at lower temperature of about 1000.degree. C. to 1050.degree. C., as compared with the temperature of the first annealing of the thermal oxide layer, thereby reducing distortions of the semiconductor substrate and reducing current leakages.

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Yongin, South Korea

Moon-Han Park