Samsung Electronics Co., Ltd.

Moon-hae Son

Jei-hwan Yoo

Jin-man Han

Choong-Sun Shin

There is provided a semiconductor memory device having a multibank in which a single large memory cell is divided into a plurality of banks without increasing power consumption and chip size. In the semiconductor memory device, a memory cell array is divided into a plurality of banks arranged alternately, and each bank includes a plurality of unit memory cell arrays. In addition, column selection lines of each bank are connected to alternate output ports of a column decoder, and the column decoder enables the column selection lines of a bank selected from the plurality of banks in response to address decoding signals and bank selection signals.

Semiconductor memory device having multibank

A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and controlling an isolation gate. The refresh row active signal is activated for a constant period. A plurality of block select signals are selectively activated when the refresh row active signal is active. The latch isolation control signal is set according to a block select signal and reset by an adjacent block select signal related to the other isolation gate connected to the same bit line sense amplifier of the block. In the step of controlling the isolation gate, when the latch isolation control signal is active, the isolation gates are turned on, and the other isolation gates connected to the same bit line sense amplifier are turned off. The isolation gate control circuit includes a plurality of latches, a plurality of block select signal drivers and a plurality of isolation gate control signal generators.

Method and circuit for controlling an isolation gate in a semiconductor

There is disclosed a semiconductor memory device that has a memory-cell array with memory cells arranged in a matrix, bit-line sense amplifiers connected to bit lines of the memory-cell array, a row address predecoder performing decoding of some of row address signals in response to a system clock, and a plurality of banks having an output line of the row address predecoder in common, includes: a row strobe buffer connected to an external system and producing a first control signal for selecting corresponding banks in response to the system clock, a row address strobe signal, and a bank selection address signal and for controlling generation of a row address sampling control signal; a row address sampling control signal generating circuit producing the row address sampling control signal in a predetermined period of time in response to generation of the first control signal produced by the row strobe buffer in order to control word-line activating and precharging operations; and a row decoder latching an output signal obtained by predecoding a row address with the output signal of the row address sampling control signal generating circuit.

Integrated circuit memory devices including a plurality of row latch

A row address control circuit for a memory device includes a row address enable signal generator, a row address buffer, a row predecoder, a row address strobe buffer, a predecoded row address sampling pulse generator, and a row decoder. The row address enable signal generator produces a row address enable signal which is enabled while a clock signal is enabled. The row address buffer receives the output of the row address enable signal generator and produces a row address signal enabled while the row address enable signal is enabled. The row predecoder receives and predecodes the output of the row address buffer and produces a predecoded row address signal. The row address strobe buffer receives the clock signal and produces a first control signal while the clock signal is enabled. The predecoded row address sampling pulse generator receives the output of the row address strobe buffer and produces a predecoded row address sampling pulse signal for selecting the predecoded row address signal while the first control signal is enabled. The row decoder receives the output of the predecoded row address sampling pulse generator and the row predecoder and has its output connected to a word line and activates the word line when the predecoded row address signal and the predecoded row address sampling pulse signal are enabled.

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Seoul, South Korea

Moon-hae Son