Samsung Electronics Co., Ltd.

Moon Gyung Kim

Dong San Jun

Sung Gu Lee

A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.

Cache allocation based on quality-of-service information

A master for transmitting data to a slave via a bus segment by segment is provided. The master includes a finite state machine (FSM) configured to receive and analyze dirty bits for first data segments to be included in a current segment among the data and to output a first selection signal and location information related to the current segment according to an analysis result and a first multiplexer configured to determine whether to output the current segment as a dirty data segment to the bus based on the first selection signal.

Master capable of communicating with slave and system including the master

A word line driving circuit for use in a semiconductor memory device having a first supply voltage terminal to which a pumping voltage higher than a supply voltage supplied from the exterior of a chip is applied and a second supply voltage terminal to which a ground voltage is applied includes a decoding circuit connected between the first supply voltage terminal and second supply voltage terminal, for receiving a decoded row address, a precharge circuit connected to an output terminal of the decoding circuit, a transfer circuit for receiving an output signal of the decoding circuit and a word line boosting signal, and a word line output circuit connected between the first supply voltage terminal and second supply voltage terminal, for driving a word line.

Word line driving circuit of a semiconductor memory device

In a selecting circuit for a memory operating mode, the circuit has a mode enable pulse generator which produces a short pulse for a mode enable pulse. A mode selecting clock generator which receives a mode enable pulse and selects a memory operating mode. The number of the mode selecting clock generator is determined by the number of memory operating mode to be used. A fuse, coupled with each of the mode selecting clock generators, is out when the corresponding mode selecting generator is selected and hence produces a mode selecting signal.

Growing community of inventors

Suwon-si, South Korea

Moon Gyung Kim