Samsung Electronics Co., Ltd.

Moon-Gi Cho

Jeong-Woo Park

Sang-Young Kim

Eun-Chul Ahn

Sun-Hee Park

Min-Ho Lee

Joo-Weon Shin

Yong-hwan Kwon

Yong-Hwan Kwon

Sang-hee Lee

Jong-bo Shim

Hwan-Sik Lim

Ui-hyoung Lee

Jong-Yun Myung

A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.

Semiconductor device having fuse pattern

A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.

Solder collapse free bumping process of semiconductor device

A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.

Multi-chip package and method of manufacturing the same

A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.

Bump structure, having concave lateral sides, semiconductor package having the bump structure, and method of forming the bump structure

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Semiconductor assembly and semiconductor package including a solder channel

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Suwon-si, South Korea

Moon-Gi Cho