Samsung Electronics Co., Ltd.

Moon Gi Cho

Heonjong Shin

Jinwoo Jeong

Deokhan Bae

Hwichan Jun

Jaeseok Yang

YoungWoo Cho

Hyeonuk Kim

Jongchan Shin

Jaeran Jang

Eryung Hwang

Chajea Jo

Hyunsoo Chung

Young Lyong Kim

In-Young Lee

Taeje Cho

Sun-Hee Park

Hwan-Sik Lim

Byungju Kang

Keum-hee Ma

Janie Hyojin Kim

Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Semiconductor devices having multi-level metallization structures

A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

Semiconductor device

Semiconductor devices

A semiconductor device and a fabricating method thereof are provided. The method includes sequentially forming an interlayer insulating layer and a hard mask layer on a substrate with first and second regions, performing a first patterning process on the hard mask layer to form first openings in the first and second regions, performing a second patterning process on the hard mask layer to form second openings in the first and second regions, and performing a third patterning process on the hard mask layer to selectively form at least one third opening in only the second region. The third patterning process includes forming a first photoresist pattern with openings on the hard mask layer, and the opening of the first photoresist pattern on the first region is overlapped with the second opening on the first region, when viewed in a plan view.

Semiconductor device and method of fabricating the same

A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.

Bump structures having an extension

Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer.

Semiconductor packages having through electrodes and methods for fabricating the same

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Anyang-si, South Korea

Moon Gi Cho