Samsung Electronics Co., Ltd.

Moo-Kyung Lee

Sunghoon Kim

Hong-soo Kim

Hwa-Kyung Shin

Jong-Ho Lim

Jaeick Son

An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.

Method for verifying a layout designed for a semiconductor integrated circuit and a computer system for performing the same

A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.

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Seoul, South Korea

Moo-Kyung Lee