Texas Instruments Corporation

Montray Leavy

Stephan Grunow

Satyavolu Srinivas Papa Rao

Noel M Russell

Kenneth D Brennan

Darius Lammont Crenshaw

Duofeng Yue

Phillip D Matz

Sameer Kumar Ajmera

Somit Joshi

Yuri E Solomentsev

The present invention provides a method for forming an interconnect on a semiconductor substrate. The method includes forming an openingover an inner surface of the opening, the depositing forming a reentrant profile near a top portion of the opening. A portion of barrieris etched, which removes at least a portion of the barrierto reduce the reentrant profile. The etching also removes at least a portion of the barrierlayer at the bottom of the opening

Contact resistance reduction by new barrier stack process

The formation of a MIM (metal insulator metal) capacitor () and concurrent formation of a resistor () is disclosed. A copper diffusion barrier () is formed over a copper deposition () that serves as a bottom electrode () of the capacitor (). The copper diffusion barrier () mitigates unwanted diffusion of copper from the copper deposition (), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface () of the deposition of copper/bottom electrode. Subsequently, layers of dielectric () and conductive () materials are applied to form a dielectric () and top electrode () of the MIM capacitor (), respectively, where the layer of conductive top electrode material () also functions to concurrently develop the resistor () on the same chip as the capacitor ().

Single mask MIM capacitor and resistor with in trench copper drift barrier

A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (). One or more feature regions are formed in the interlayer dielectric layer (). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer ()). A first anneal is performed that promotes grain growth of the first conductive layer (). An additional conductive layer is formed on the first conductive layer () and an additional anneal is performed () that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device ().

Partial plate anneal plate process for deposition of conductive fill material

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McKinney, TX, United States of America

Montray Leavy