Raytheon Company

Monte R Sanchez

Brandon William Pillans

Sankerlingam Rajendran

Thomas A Hanft

Douglas R Gentry

Susan M Eshelman

Robert T Manley

An interconnect is provided that can comprise a recess formed in a body where the recess comprises an axial end wall and a side wall extending from the axial end wall. The interconnect can also comprise a distributed metallized layer disposed on the axial end wall and the side wall and a conductive compliant (CC) plug disposed within the recess to interface with the metallized layer. The CC plug can be configured to establish an electrical connection between a conductive pad disposed on the recess and a male conductive element inserted into the recess via the metallized layer.

Interconnect and method for manufacturing the same

Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Heterogeneous chip integration with low loss interconnection through adaptive patterning

Growing community of inventors

Murphy, TX, United States of America

Monte R Sanchez