Micron Technology Incorporated

Micron Semiconductor, Inc.

Monte Manning

Charles H Dennison

Shubneesh Batra

J Brett Rolfson

Sanjay K Banerjee

John Damiano, Jr

Tyler A Lowrey

Charles L Turner

LeTien Jung

Howard E Rhodes

Roger R Lee

Todd R Abbott

Ruojia R Lee

Steve V Cole

A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer over the substrate; c) providing a first insulating material layer over the first conductive layer; d) etching through the first insulating layer and the first conductive layer to the substrate to both form a plurality of first conductive lines from the first conductive layer and provide a plurality of grooves between the first lines, the first lines being capped by first insulating layer material, the first lines having respective sidewalls; e) electrically insulating the first line sidewalls; and f) after insulating the sidewalls, providing the grooves with a second conductive material to form a plurality of second lines within the grooves which alternate with the first lines. Integrated circuitry formed according to the method, and other methods, is also disclosed.

Integrated circuitry and a semiconductor processing method of forming a series of conductive lines

Methods of forming thin film transistors, and transistors therefrom, are provided where at least one of the source or drain region is conductively doped while conductivity doping of the channel region is prevented without any masking by any separate masking layer. Methods include, providing a substrate having a conductive node; providing a first dielectric layer, a gate layer over the first layer and a second dielectric layer over the gate layer; providing a contact opening through the first and second layers and the gate layer, the opening defining projecting sidewalls; providing a gate dielectric layer within the opening; providing a layer of semiconductive material over the second layer, against the gate dielectric layer and in electrical communication with the node; the material defining a channel region; and conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region.

Thin film transistor

Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filed with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry

An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Methods of forming transistors

Integrated circuitry includes a semiconductive substrate, an insulative material over the semiconductive substrate, and a series of alternating first and second conductive lines, the first and second lines being spaced and positioned laterally adjacent one another over the insulating layer. At least some of the laterally adjacent conductive lines may have different cross-sectional shapes in a direction perpendicular to the respective line. Alternatively, or in addition, individual second series conductive lines may be spaced from adjacent first series conductive lines a distance that is less than a minimum width of the first series lines.

Integrated circuitry conductive lines

A method of forming a thin film transistor over a substrate is provided whereby at least one of the source region or the drain region is conductively doped while preventing conductivity doping of the channel region without any masking of the channel region occurring by any separate masking layer. A method includes, a) providing a substrate having a node to which electrical connection is to be made; b) providing a first electrically insulative dielectric layer over the substrate; c) providing an electrically conductive gate layer over the first dielectric layer; d) providing a second electrically insulative dielectric layer over the electrically conductive gate layer; e) providing a contact opening through the second dielectric layer, the electrically conductive gate layer and the first dielectric layer; the contact opening defining projecting sidewalls; f) providing a gate dielectric layer within the contact opening laterally inward of the projecting sidewalls; g) providing a layer of semiconductive material over the second dielectric layer and within the contact opening against the gate dielectric layer and in electrical communication with the node; the semiconductive material within the contact opening defining an elongated and outwardly extending channel region the electrical conductance of which can be modulated by means of the adjacent electrically conductive gate and gate dielectric layers; and h) conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region of a thin film transistor. Thin film transistor construction are also disclosed.

Methods of forming thin film transistors

A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion. The outer portion has a terminus and the inner portion extends laterally away from the outer portion terminus and generally toward the node location. The inner portion is in electrical communication with the node location.

Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry

Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Methods of forming diodes

Methods of forming integrated circuitry

Integrated circuitry

The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

Growing community of inventors

Kuna, ID, United States of America

Monte Manning