Zilog, Inc.

Monte J Dalrymple

Don Smith

Lois F Brubaker

Craig A MacKenna

Phillip D Verinsky

A device for automatic transfer of status information concerning data blocks between a microprocessor controlled system and a peripheral device where a direct memory access controller (DMA) is used for transferring data. The status information concerning a certain data block is stored in status registers where the status information is received from either the microprocessor controlled system or the peripheral device. The DMA controls the transfer of data between the two systems where the blocks of data are stored in a FIFO. Each data block contains at its end an end of data indicator. A state machine and counter responds to the end of data indicator of a data block upon the completion of the transfer of the data block to generate an enabling signal for transferring the status information from the register as if it were part of the data block. This is performed in a manner transparent to the DMA and the microprocessor to obviate the need of microprocessor intervention.

System for the automatic transfer of message status in digital data

In a system for transmitting data employing a transmit FIFO and a transmitter, the quantity of data that has been written into the FIFO is monitored and a transmitter is caused to begin transmitting data from the memory when the quantity of data in the memory exceeds a predetermined level. An end of frame condition is detected and a transmitter is caused to begin transmitting data upon receipt of end of frame signal even though the quantity of data in the memory does not exceed the predetermined level.

Technique for eliminating data transmit memory underruns

By monitoring various combinations of control signals generated by a microprocessor in a computer system in the first operational cycles after it is reset, a peripheral circuit sets itself to respond appropriately to control signals from the microprocessor according to any of several different protocols. For example, an instruction from the microprocessor to write to or read from the peripheral circuit is implemented over two control lines with one of several possible protocols. The circuit determines which protocol is being used each time the system is initialized and thereafter knows when a read or write operation is being performed. Another example is the different wait or acknowledge protocols that various microprocessors use. The peripheral circuit can thus be used with a variety of microprocessors without having to provide sets of pins dedicated to each signal protocol used by available microprocessors, and without the necessity to load a configuration register in the peripheral circuit by the microprocessor as part of the initialization process.

Technique for automatically adapting a peripheral integrated circuit for

A microprocessor formed on a single integrated circuit chip has separate sets of terminals providing read and write control timing signals to external memory and input-output devices. The memory control timing signals are generated at a rate as high as the memory devices will allow. The input-output device timing signals are provided at a rate as high as the input-output devices will allow, usually significantly lower rate than that of the memory devices. This then allows the memory transactions to occur at a rate that does not need to be reduced because of slower input-output devices in the same system. The need for external logic is significantly reduced by providing the memory timing signals in a form that is actually input to the memory devices, and by including a capability of providing timing signals to a number of different types of input-output devices having different control signal timing protocol requirements. A computer system using such a microprocessor unit is also described.

Integrated microprocessor unit generating separate memory and

A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes. The various hardware options responsive to the hardware parameters include allowing for various bus interfaces, trimming the time constant of an analog RC circuit which provides internal bus timing strobes, switching internal timing strobes to external pads for output, switching external timing strobes from external pads to replace the internal strobes, and floating the outputs of all output pad drivers for junction leakage tests.

Device and method for programming critical hardware parameters

A bus-oriented integrated circuit chip containing devices such as Receive and Transmit FIFO's further includes a testing circuit for testing normally inaccessible internal nodes in a FIFO device. The testing circuit includes test mode control register for storing the externally supplied test addresses of selected internal nodes of a FIFO device. A decoder, responding to a test command from a host microprocessor, selects the test addresses from the test mode control register and supplies them instead of other addresses to an internal address bus. A test decoder responds only to the test addresses on the internal address bus for enabling the transfer of data between the selected internal nodes and a data bus, thereby enabling bus access of the normally inaccessible internal nodes of a FIFO device.

System for testing internal nodes in receive and transmit FIFO's

A peripheral device containing a control circuit with internal timing which enables it to independently adjust the timing of an interrupt acknowledge cycle. The circuit senses a timing signal from the CPU and asserts a control signal to suspend the operation of the CPU for a predetermined period of time. The predetermined period of time is customized to the peripheral so that when the CPU is re-activated and reads from the bus, a valid interrupt vector will have been put out by the peripheral.

Device for timing interrupt acknowledge cycles

A digital electronic circuit for incrementing or decrementing a binary word one count at a time. Such a circuit has an application as an address counter wherein a block of addresses in memory are stepped through one at a time. Such an address counter is found, for example, in a direct memory access (DMA) computer system integrated circuit. The count is incremented or decremented by adding or subtracting, respectively, a one from the current binary count in order to obtain a new count. A carry chain used as part of such addition circuit is separated into at least two parts and a look-ahead chain is added to work in conjunction with the carry chain to anticipate certain changes without having to wait for the carry chain to be fully sequenced. This technique reduces the time necessary to calculate the carries in the addition or subtraction process and further allows some parallel operation of the two parts of the carry chain. In a preferred implementation, the carry chain, look-ahead chain and an adder are formed in repeatable, interconnected cells wherein each chain stage has essentially a single gate and in which each cell includes the gates of two non-adjacent stages of each of the chains. This allows the circuit to be constructed in CMOS, minimizes the number of gates, and thus gate delays, and makes it easy to lay out a circuit.

Carry chain incrementer and/or decrementer circuit

A universal bus interface compatible with a number of different bus interface protocols is disclosed. In any given application, the control lines carrying signals by a processor are connected to the appropriate interface signal pins of the bus interface with all unused interface signal pins tied to their inactive level. The bus interface derives a strobe signal from the timing information carried by the control lines from the processor. The strobe signal derived by the interface controls data flow within a peripheral device or data flow between a peripheral device and a processor without the aid of any clock signals. A NAND-gate is used in the interface to derive the strobe signal from processor control signals. The NAND-gate comprises a number of inverters arranged in parallel each located close to an interface input pin to eliminate the need for any logic for driving the gate. The outputs of the inverters are connected to a common node to provide the strobe signal. When the output of an inverter falls from high to low, a feedback loop causes the output of the inverter to be in a high impedance state so that the low state of the output of such inverter does not prevent the NAND-gate output from being pulled to the high state by the output of a different inverter.

Universal bus interface

The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.

System for testing internal nodes

The fill or empty level of a FIFO is detected and compared to a first request level for the direct memory access controller or the coprocessor. When the fill or empty level exceeds the first request level, notification to the DMA or the coprocessor is generated. The fill or empty level is also compared to a second request level and when such level exceeds second request level, notification to the CPU is generated. Thus, in most cases, the DMA or coprocessor is able to obtain control of the bus before the request level for CPU interrupt is reached, thereby preventing wasteful CPU intervention as well as FIFO overruns and underruns. In case the DMA or coprocessor is unable to obtain control of the bus before the request level for CPU interrupt is reached, CPU intervention is available as a last resort.

System for providing notification of impending FIFO overruns and

In the serializer for converting parallel data into serial data, where the parallel data comprises normal characters all of the same length and a last character of a different length, the characters are each tagged by an extra bit as it enters a FIFO. This tag bit indicates the length of the character and is shifted along with the character as the character is shifted through the FIFO. The normal character length and the length of the last character are stored. As a character emerges from the FIFO, its tag bit identifies it as a normal character or as the last character. Such tag bit is used to select the correct character length in a counter. The character is loaded in a shifter which is controlled by the counter. Therefore, the shifter is controlled by the counter to shift the correct number of times in order to shift the character into a serial bit stream. Since each character carries along with it a bit which indicates its character length, the CPU is not called upon to intervene in a time critical manner to change the character length in the counter in order to correctly control the shifting of the shifter. Hence messages of arbitrary bit length can be transmitted without the normal CPU intervention at the end of the message.

Serializer system with variable character length capabilities

From an input signal, a buffer circuit derives an output signal which changes in logic state in synchronism with the rising edges of a first clock and whose value follows the input signal but in opposite logic state. The first clock directly drives the buffer output through a first transistor whose gate is controlled by the output of a NOR-gate. The buffer output is connected to ground through two FET's whose gates are controlled respectively by the first clock and the input signal as sampled by a second clock. The buffer output after being delayed and the input signal as sampled by the second clock are applied to the inputs of the NOR-gate. By adding an FET between the gate of the first transistor and the output of the NOR-gate the bootstrap action caused by the gate-drain parasitic capacitance of the first transistor reduces the delay between the rise of the buffer output and the rising edge of the first clock. A holding circuit may be used to hold the value of the buffer output despite changes in the states of the clocks.

High speed clocked, latched, and bootstrapped buffer

A circuit and technique provided as part of an integrated circuit for assuring that the circuit's many bistable elements are properly initialized into their desired state when the power is turned on to the circuit. An initialization signal is developed for forcing the bistable element to their pre-determined states as the voltage of the power source is brought up from zero to its full value. This is accomplished by using another bistable element to monitor the rise in the supply voltage and turn off the initialization signal only after the supply voltage has risen well above the threshold voltage of the various bistable elements on the circuit. Hysteresis is provided in order to prevent the initialization signal from turning on if the supply voltage temporarily dips below that at which the monitor element turns off the initiation signal.

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Fremont, CA, United States of America

Monte J Dalrymple