Freescale Semiconductor,inc.

Nxp Usa, Inc.

Other

Monte Gene Miller

Joseph Staudinger

Paul Richard Hart

Abdulrhman M S Ahmed

Alexander James Elliott

Yun Wei

Nicholas J Spence

Jeffrey Dale Crowder

Lakshminarayan Viswanathan

Matthias Passlack

Bruce McRae Green

Charles E Weitzel

Margaret A Szymanowski

Olin L Hartin

David F Abdo

Ricardo Uscola

Ellen Y Lan

Marcus R Ray

Philip Li

Power amplifier (PA) packages, such as Doherty PA packages, containing multi-path integrated passive devices (IPDs) are disclosed. In embodiments, the PA package includes a package body through which first and second signal amplification paths extend, a first amplifier die within the package body and positioned in the first signal amplification path, and a second amplifier die within the package body and positioned in the second signal amplification path. A multi-path IPD is further contained in the package body. The multi-path IPD includes a first IPD region through which the first signal amplification path extends, a second IPD region through which the second signal amplification path extends, and an isolation region formed in the IPD substrate a location intermediate the first IPD region and the second IPD region.

Power amplifier packages containing multi-path integrated passive devices

A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.

Multiple-stage power amplifiers and amplifier arrays configured to operate using the same output bias voltage

Embodiments of an amplifiers and integrated circuits include a first transistor and a second transistor. A second current-carrying terminal of the first transistor may be coupled to a first current-carrying terminal of the second transistor and the control terminal of the second transistor may be coupled to a low impedance alternating current (AC) potential node. A bias network that includes a first circuit element and a second circuit element couples the second current-carrying terminal of the second transistor to the control terminal of the second transistor. The first circuit element may be configured to apply a portion of a potential at the second current-carrying terminal of the second transistor to the control terminal of the second transistor, and the second circuit element may be coupled between the control terminal of the second transistor and a fixed potential.

Amplifiers and related integrated circuits

An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.

Modifiable signal adjustment devices for power amplifiers and corresponding methods and apparatus

A method of making a mounted gallium nitride (GaN) device includes obtaining a device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer. The GaN layer is processed to form an active layer of active devices and interconnect over the GaN layer. After the step of processing the GaN layer, a gold layer is formed on the silicon layer. The device structure is attached to a heat sink structure using the gold layer. The mounted GaN device includes the SiC layer over the polysilicon layer and the GaN layer over the SiC layer. The active layer is over the GaN layer.

Method of making a mounted gallium nitride device

In one embodiment, a semiconductor device () includes a buffer layer () formed over a substrate (). An AlGaAs layer () is formed over the buffer layer () and has a first doped region () formed therein. An InGaAs channel layer () is formed over the AlGaAs layer (). An AlGaAs layer () is formed over the InGaAs channel layer (), and the AlGaAs layer () has a second doped region formed therein. A GaAs layer () having a first recess is formed over the AlGaAs layer (). A control electrode () is formed over the AlGaAs layer (). A doped GaAs layer () is formed over the undoped GaAs layer () and on opposite sides of the control electrode () and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device () maintains linear operation over a wide temperature range.

pHEMT with barrier optimized for low temperature operation

A thin GaAs Substrate can be provided with a copper back-metal layer to allow the GaAs Substrate to be packaged using conventional plastic packaging technologies. By providing the GaAs Substrate with a copper back-metal layer, the GaAs Substrate can be made thinner than 2 mils (about 50 microns), thereby reducing heat dissipation problems and allowing the semiconductor die to be compatible with soft-solder technologies. By enabling the semiconductor die to be packaged in a plastic package substantial cost savings can be achieved.

Method for manufacturing thin GaAs die with copper-back metal structures

A planar conductor has a first port and a plurality of second ports. A conductive planar region is electrically coupled between the first port and the plurality of second ports. The planar region includes a first region adjacent to the first port, a third region adjacent to the second ports, and a second region between the first region and the third region. Each region has a corresponding greatest width. The greatest width of the second region is less than each of the greatest widths of the first and third regions. Irregular lateral edges of the planar conductor conduct prevent concentrations of an electrical signal at the lateral edges to more uniformly drive devices that are connected to the planar conductor.

Slotted planar power conductor

Thin GaAs die with copper back-metal structure

A power amplifier device having a conductive structure overlying a dielectric layer. The conductive structure has a first conductive structure portion that is substantially electrically isolated from a second conductive structure portion. A first plurality of bond wires couple the first conductive structure portion to an amplifying device, while a second plurality of bond wires couple the second conductive structure portion to the amplifying device.

Growing community of inventors

Gilbert, AZ, United States of America

Monte Gene Miller