Intel Corporation

Monis Rahman

Tse-Yu Yeh

Mircea Poplingher

Ashish V Choubal

Wenliang Chen

Carl C Scafidi

Mitchell Alexander Poplingher

A microprocessor is disclosed. The microprocessor includes a branch prediction table that has at least one branch entry. The at least one branch entry includes a prediction field to indicate whether a branch is predicted taken. The at least one branch entry also includes a history register that stores history information. Moreover, the branch prediction table includes a prediction update logic that updates the prediction field and the history register except when a branch is strongly predicted statically.

Optimized branch predictions for strongly predicted compiler branches

A method and apparatus for generating respective branch predictions for first and second branch instructions, both indexed by a first instruction pointer, is disclosed. The apparatus includes dynamic branch prediction circuitry for generating a branch prediction based on the outcome of previous branch resolution activity, as well as static branch prediction circuitry configured to generate a branch prediction based on static branch prediction information. Prediction output circuitry, coupled to the both the dynamic and static branch prediction circuitry, outputs the respective branch predictions for the first and second branch instructions in first and second clock cycles to an instruction buffer (or 'rotator'). Specifically, the prediction output control circuitry outputs the branch prediction for the second branch instruction in the second clock cycle and in response to the initiation of a recycle stall during the first clock cycle. The receipt of the predictions and their corresponding branch instructions at the instruction buffer is thus synchronized, and the opportunity of generating a prediction for the second branch instruction is not lost.

Method and apparatus for generating branch predictions for multiple

Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit which identifies related data units by identifying a probability that the related data units may be successively read from the cache memory. A second circuit within the allocation circuitry allocates the corresponding entries in each of the ways to the related data units, so that related data units are stored in a common set of entries. Accordingly, the related data units will be simultaneously outputted from the set-associative cache memory, and are thus concurrently available for processing. The invention may find application in allocating entries of a common set in a branch prediction table (BPT) to branch prediction information for related branch instructions.

Growing community of inventors

San Jose, CA, United States of America

Monis Rahman