Sandisk Technologies Inc.

Lam Research Corporation

Monica Titus

Senaka Kanakamedala

Raghuveer S Makala

Alex Paterson

Rahul Sharangpani

Gowri Kamarthy

Roshan Jayakhar Tirukkonda

Harmeet Singh

Yoshie Kimura

Thorsten B Lill

Yao-Sheng Lee

Adarsh Rajashekhar

Vahid Vahedi

Saravanapriyan Sriraman

Nicolas Gani

Radhika C Mani

Noel Sun

Helene Del Puppo

Do Young Kim

Jen-Kan Yu

Ting-Ying Chung

Zhixin Cui

Meihua Shen

Baosuo Zhou

Ramy Nashed Bassely Said

Yifeng Zhou

John Hoang

Chih-Yu Lee

Katsufumi Okamoto

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack and cavities are formed in the hard mask layer. A cladding liner is formed on sidewalls of the cavities in the hard mask layer. Via openings are formed through each layer within the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavities through the alternating stack.

A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

A method includes forming an alternating stack of first and second layers, forming a composite hard mask layer over the alternating stack, forming openings in the hard mask, and forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the openings in the composite hard mask layer through the alternating stack. The compositing hard mask includes a first cladding material layer which has higher etch resistance than upper and lower patterning films of the composite hard mask.

An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack. Optionally, an additional hard mask layer can be formed over the hard mask layer. A photoresist layer is applied and patterned, and cavities are formed in the hard mask layer by performing a first anisotropic etch process that transfers a pattern of the openings in the photoresist layer through the hard mask layer. Via openings are formed through an upper portion of the alternating stack by performing a second anisotropic etch process. A cladding liner can be optionally formed on sidewalls of the cavities in the hard mask layer. The via openings can be vertically extend through all layers within the alternating stack by performing a third anisotropic etch process.

An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed on a top surface of the patterning film and sidewalls of the openings in the pattering film. The via openings can be vertically extended through the semiconductor material layer at least to a bottom surface of the semiconductor material layer by performing a second anisotropic etch process employing the cladding liner as an etch mask.

A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof

A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer to a conductive structure that can be a node of the at least one first semiconductor device or one of lower-level metal interconnect structures. The interconnection via structure includes a transition metal layer and a fluorine-doped filler material portion in contact with the transition metal layer, composed primarily of a filler material selected from a silicide of the transition metal element or aluminum oxide, and including fluorine atoms.

Three dimensional semiconductor device containing composite contact via structures and methods of making the same

Methods, systems, and computer programs are presented for controlling gas flow in a semiconductor manufacturing chamber. The method includes flowing a reactant gas thorough an inner feed and a tuning gas through an outer feed surrounding the inner feed, such that the gases do not mix until both are introduced in the chamber. Further, the flow of the reactant gas is convective, and the flow of the tuning gas is directed at an angle from the direction of the reactant gas, providing a delivery of the tuning gas in closer proximity to the RF power before further mixing with the reactant gas. Radio frequency power is provided to the electrode to ignite a plasma using the reactant and tuning gases. The diffusive flow of the tuning gas enables the tuning gas to be dissociated by the RF power allowing for control of the local residence time variation and preferential spatial dissociation patterns with respect to the local residence time of the reactant gas. The introduction of the gases into the chamber without pre-mixing imparts control of etch uniformity across the surface of the substrate during etching.

Gas reaction trajectory control through tunable plasma dissociation for wafer by-product distribution and etch feature profile uniformity

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Internal plasma grid for semiconductor fabrication

Methods, systems, and computer programs are presented for controlling gas flow in a semiconductor manufacturing chamber. The method includes flowing a reactant gas thorough an inner feed and a tuning gas through an outer feed surrounding the inner feed, such that the gases do not mix until both are introduced in the chamber. Further, the flow of the reactant gas is convective, and the flow of the tuning gas is directed at an angle from the direction of the reactant gas, providing a delivery of the tuning gas in closer proximity to the RF power before further mixing with the reactant gas. Radio frequency power is provided to the electrode to ignite a plasma using the reactant and tuning gases.

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Internal plasma grid applications for semiconductor fabrication

A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

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Sunnyvale, CA, United States of America

Monica Titus