Nxp B.v.

Nxp Usa, Inc.

Mojtaba Ashourloo

John M Pigott

Olivier Trescases

Hendrik Johannes Bergveld

Gerard Villar Piqué

Alaa Eldin Y El Sherif

Venkata Raghuram Namburi

There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw, Vsw, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw[n&#x2212;1], Vsw[n&#x2212;1]) and in a next subsequent operating cycle (Vsw[n], Vsw[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Fault detection in hybrid DC-DC power convertors

A level shifter comprising: a translation circuit having two input lines and two output lines and configured to receive a differential signal in a low-voltage domain on the two input lines and provide a second differential signal, being a copy of the first differential signal, in a high-voltage domain on the two output lines; and a combiner circuit configured to convert the second differential signal into a single-ended signal at a high-voltage shifter output; wherein the combiner circuit comprises a two-input Muller C-element circuit wherein one input is inverted. Corresponding methods are also disclosed.

Level shifter and a method of level shifting a signal

Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Distributed control of a multiphase power converter

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Toronto, Canada

Mojtaba Ashourloo