Xilinx, Inc.

Vidatronic, Inc.

Advanced Micro Devices Corporation

Oak Technology, Inc.

Moises Emanuel Robinson

Shahriar Rokhsaz

Marwan M Hassoun

Ahmed Younis

Mohamed Mostafa Saber Aboudina

Michael A Nix

Bernard L Grung

Faisal Abdellatif Elseddeek Ali Hussien

Brian Taylor Brunn

Jinghui Lu

Mohamed Ahmed Mohamed El-Nozahi

Sameh Assem Ibrahim

David Erich Tetzlaff

Earl E Swartzlander, Jr

Tim J Dupuis

Steven P Young

F Erich Goetting

William C Black

Michael J Gaboury

Carlin D Cabler

Firas Najeh Abughazaleh

Xiaojie He

Sonu Arora

Anil Kumar

Stephen D Anderson

Normand T Lemay, Jr

Jose Silva-Martinez

Anand Veeravalli Raghupathy

Sameh Ahmed Assem Ibrahim

Yiqin Chen

Michael Ren Kent

Yvette P Lee

Mauricio Zavaleta

Sameh Ahmed Assem Mostafa Ibrahim

Mostafa Mohamed Hesham Kamel Toubar

He Hu

Faisal Abdellatif Elseddeek Hussien

John Tabler

Kazi S Hossain

Earl E Swartzlander

A technique for adjusting a power supply for a device is provided. The technique includes detecting a low-power trigger for a device; switching a power supply for the device from a high-power power supply to a low-power power supply; detecting a high-power trigger for a device; and switching a power supply for the device from the low-power power supply to the high-power power supply, wherein the high-power power supply consumes a larger amount of power than the low-power power supply, and wherein the high-power power supply provides a greater amount of noise reducing and a greater tolerance to temperature differences than the low-power power supply.

Power delivery system having low- and high-power power supplies

A bandgap reference circuit includes a circuit for high-order temperature curvature compensation; and a circuit for low output impedance and current drive capability, wherein an output voltage of the bandgap reference circuit can be independently adjusted to be either above or below a silicon bandgap voltage without impacting temperature curvature.

Scalable low output impedance bandgap reference with current drive capability and high-order temperature curvature compensation

A silicon based (e.g., SiGe, CMOS, or BiCMOS) transmitter includes an algorithm that strategically segment and pre-distort the input signal according to its power; a reconfigurable power amplifier (PA) having a plurality of PA sections, wherein the plurality of PA sections comprise discrete weighted transistor arrays that are digitally turned OFF or ON according to a magnitude of an input signal; an impedance matching network equipped with a common-mode feedback (CMFB) mechanism configured to reduce common-mode glitches at an output of the PA due to ON/OFF manipulations of the PA segments; and a 1:N transformer, which comprises a capacitive matching engine and a power detector, disposed between the impedance matching network and the reconfigurable linear PA.

Apparatus and methods for power efficient CMOS and BiCMOS transmitters suitable for wireless applications

An automatically reconfigurable Buck-Boost DC-DC converter having an input supply and an output voltage includes a linear regulator (LDO) for Buck configuration; a switched-capacitor DC-DC converter; a capacitor and switch array, and a gain selector to switch between the linear regulator (LDO) when an output DC level is higher than an input DC level (Buck configuration) and the switched-capacitor DC-DC converter when the output DC level is lower than the input DC level (Boost configuration).

Automatically reconfigurable buck-boost DC-DC converter with shared capacitors

A method to adjust the load transient regulation of a low drop-out (LDO)/load switch linear voltage regulator (LVR) with an n-type pass element having an open loop transfer function, including determining during a load transient event if the gate of the pass&#x2014;element goes lower than a scaled value of the output voltage or a constant voltage level, generating a control signal that controls a current sink block if the gate voltage of the pass element is lower than the output voltage, and enabling a current sink block that is controlled by the control signal and connecting the output of the current sink block to the output of the LVR.

Circuit to improve load transient behavior of voltage regulators and load switches

An architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture method support optionally determining during a power-up phase and by using a load detection circuit, the estimated load parameters that represents at least one selected from a group consisting of: the load time constant and the load resistor at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output load parameters, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is adjusted based on the estimated load parameters.

LDO and load switch supporting a wide range of load capacitance

A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

High voltage protection circuit for non-tolerant integrated circuit

A soft-start/soft-stop (SS) controller for a voltage regulator. The SS controller includes a power up/down detector configured to perform at least one selected from a group consisting of detecting a power on condition of the voltage regulator to determine a start-up time period and detecting a power off condition of the voltage regulator to determine a shut-down time period, and a ramped reference voltage signal generator configured to perform at least one selected from a group consisting of increasing a voltage level of a ramped reference voltage signal using a pre-determined ramp-up rate during the start-up time period and decreasing the voltage level of the ramped reference voltage signal using a pre-determined ramp-down rate during the shut-down time period, wherein the ramped reference voltage signal is supplied to the voltage regulator for controlling an output voltage level of the voltage regulator.

Voltage regulators with improved startup, shutdown, and transient behavior

A method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The method includes determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.

A method and apparatus for a transmitting entity within a micro-area network to establish a data transmission within the network includes processing that begins by determining the identity of a target entity within the micro-area network. The processing then continues by determining transmission characteristics of at least one communication path between the transmitting entity and target entity of the micro-area network. The processing then continues by determining a transmission convention based on the transmission characteristics. The processing then continues by providing the transmission convention to the target entity.

Method and apparatus for configuring data transmissions within a micro-area network

According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.

Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit

A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model provides one spare transceiver per group of primary transceivers, whereby reconfiguration of the IC isolates the defective transceiver and configures the replacement transceiver for operation in its place. A multiple error correction model is also provided, whereby multiple replacement transceivers may be configured to replace multiple defective transceivers. The replacement mechanism may occur during various phases of the IC, such as during wafer testing, final testing, or post-deployment testing.

Method and apparatus for a redundant transceiver architecture

A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a first P-channel transistor coupled between a voltage supply and a first VCO output, where a gate of the first P-channel transistor is coupled to the first output of the first n-channel latch; a first programmable resistor circuit coupled between the first VCO output and the first output of the first n-channel latch; and a second n-channel latch coupled to the first VCO output.

Voltage controlled oscillator

A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump () provides a current signal (I) that is first conducted by a resistor () of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor () of the RC network from node (). A second current path multiplies the current conducted by capacitor () by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor ().

Method and apparatus for capacitance multiplication within a phase locked loop

A method and apparatus for transceiving data in a micro-area network includes processing that begins by obtaining a data unit for transmission by a first data transceiving entity of a micro area network. The processing then continues when the first data transceiving entity formats the payload data using a first transmission format convention. The first data transceiving entity also formats the overhead data using a second transmission formatting convention to produce formatted overhead data. The formatting of the overhead data and/or payload data may include encoding and/or modulating the data. The processing continues when the first data transceiving entity transmits the formatted payload data and the formatted overhead data to at least one target entity within the micro-area network. The process continues when a target entity receives the formatted payload data and the formatted overhead data. The target entity then deformats the formatted payload data using the first transmission format convention to recapture the payload data and deformats the formatted overhead data using the second transmission format convention to retrieve the overhead data. The target entity then reconstructs the data unit from the retrieved payload data and the retrieved overhead data.

Growing community of inventors

Austin, TX, United States of America

Moises Emanuel Robinson