Mobileye Technologies Limited

Other

Mobileye Vision Technologies Ltd.

Mois Navon

Emmanuel Sixsou

Roman Sajman

Yosef Kreinin

Gil Israel Dogon

Yosi Arbeli

Emmanuel Sixou

Yossi Kreinin

An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating addresses of the memory over the multiple image frames. The addresses may be calculated over the image frames based upon an image parameter. The image parameter may specify which of the image frames are processed simultaneously. A scalar processor may be attached to the vector processor. The scalar processor provides the image parameter(s) to the address generator for address calculation over the multiple image frames. An input register may be attached to the vector processor. The input register may be adapted to receive a very long instruction word (VLIW) instruction. The VLIW instruction may be configured to transfer only: (i) parameters for image processing calculations over the image frames by the ALU units and (ii) a single bit to the address generator.

Hardware to support looping code in an image processing system

A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to program the computing elements with task descriptors and the computing elements are configured to receive the task descriptors and to perform a computation based on the task descriptors. The task descriptors include a field which specifies a breakpoint state of the computing element. A system level event status register (ESR) attaches to and is accessible by the CPU and the computing elements. Each of the computing elements has a comparator configured to compare the present state of the computing element to the breakpoint state. The computing element is configured to drive a breakpoint event to the event status register (ESR) if the present state of the computing element is the breakpoint state. Each of the computing elements has a halt logic unit operatively attached thereto, wherein the halt logic unit is configured to halt operation of the computing element. The ESR is configurable to drive a breakpoint event to the halt logic units to halt at least one of the computing elements other than the computing element driving the breakpoint event.

System on chip breakpoint methodology

A system for processing an image including multiple pixels and intensity data thereof. An image memory is adapted for storing the image. An arithmetic core is connectible to the image memory and adapted for inputting the intensity data. The arithmetic core includes a multiple function processing units. One or more of the function processing units includes (i) a processing core adapted for computation of a function of the intensity data and for producing results of the computation, (ii) a first and (iii) a second accumulator for summing the results; and storage adapted to store the results. The function processing units are configured to compute the functions in parallel and sum the results simultaneously for each of the pixels in a single clock cycle.

Multi-function summing machine

An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical. The processing circuitry based on the logical output, processes first any identical address operands prior to writing the updated datum into the at least one register so that a new instance of the command begins processing by the processing circuitry on a consecutive clock pulse and the command throughput is one command per clock pulse.

ELUT: enhanced look-up table signal processing

A storage buffer attached to an image processor for stereo image processing. The processor compares a first image and a second image. The storage buffer stores image data of the second image. The storage buffer includes: a data-shifting-hardware mechanism which while the processor compares a patch of the first image to a swath of the second image, the data shifting mechanism using hardware within the storage buffer shifts at least a portion of the swath within the storage buffer. The data-shifting hardware mechanism includes preferably digital multiplexers with respective selectable inputs from adjacent and non-adjacent columns of data within the storage buffer and selectable inputs from adjacent rows of data within the storage buffer.

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Efrat, Israel

Mois Navon