Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

Mohyee Mikhemar

Hooman Darabi

Ahmad Mirzaei

David Patrick Murphy

Amir Hadji-Abdolhamid

Alvin Lin

Tirdad Sowlati

Wei-Hong Chen

Sudharshan Srinivasan

Bevin George Perumana

Arya Behzad

Rahul Magoon

Masoud Kahrizi

Andrew John Blanksby

Meng-An Pan

Hao Fang Wu

Michael (Meng-An) Pan

Ahmed Sayed

An system includes a port to receive a number of bits at a first frequency. One or more cells generate a signal for a channel with a channel frequency that is N times greater than the first frequency. The cells transmit at a second frequency that is M times greater than the first frequency but is smaller than the channel frequency. Interface links are coupled between a portion of the input bits of the port and the one or more cells and the portion of the input bits is encoded by thermometer coded T bits such that each one of the T bits is encoded by M repeated parallel bits having a value of a respective T bit. Each interface link includes M interface lines between each T bit and each first cell, and M is smaller than N to reduce the number of interface lines for the T bits.

Hybrid rate interface to reduce power consumption and area in high-speed DACs and digital transmitters

A transmitter includes a first digital-to-analog converter (DAC) circuit consisting of a first set of unary cells to mix a first set of digital input data with a first clock signal. A second DAC circuit includes a second set of unary cells to mix a second set of digital input data with a second clock signal. A third circuit provides signals to the first DAC circuit and the second DAC circuit to implement an assignment scheme to assign either an in-phase (I) component or a quadrature (Q) component to the first set of unary cells and the second set of unary cells. Based on the assignment scheme, the first set of digital input data include I-data and Q-data, and the second set of digital input data include I-data and Q-data.

Dynamic assignment with phase-preserving clipping technique for digital transmitters and power amplifiers

The present disclosure describes a system that can include an antenna; a receive (Rx) path coupled to the antenna; and a transmit (Tx) path comprising a balun; and a radio frequency (RF) attenuator comprising a first port and a second port, the balun coupled to the first port, the antenna coupled to the second port. The RF attenuator can include a first switch coupled between the first port and the second port; a second switch and a first attenuator coupled to each other in series between the first port and the second port, the first attenuator having a first attenuator value; and a third switch and a second attenuator coupled to each other in series between the first port and the second port, the second attenuator having a second attenuator value greater than the first attenuator value of the first attenuator.

Systems and methods for controlling transmission of power using attenuation

Disclosed herein are related to systems and methods for correcting non-linearity due to duty cycle error. In one aspect, a system includes a mixer configured to up-convert transmission (Tx) data, a coefficient calibrator configured to select a target value of a coefficient based on a measurement of an interference signal due to non-linearity of the mixer, and an interference canceller coupled to the coefficient calibrator and the mixer. In some embodiments, the interference canceller is configured to generate compensated Tx data based on the Tx data and the selected target value of the coefficient and provide the compensated Tx data to the mixer. In some embodiments, the compensated Tx data corrects for the non-linearity of the mixer.

Digital transmitter with duty cycle correction

Disclosed herein are related to systems and methods for selectively disabling current steering circuitries. In one aspect, the system includes a balun including a first inductor and a second inductor, a first current steering circuit coupled to the first inductor, a second current steering circuit coupled to the first inductor, and a controller coupled to the first current steering circuit and the second current steering circuit. In one aspect, the controller is configured to, based on input data having a first state, apply a first signal and a second signal having a first level to the first current steering circuit and a third signal and a fourth signal having the first level to the second current steering circuit to disable a first current through the second inductor, a second current through the first current steering circuit, and a third current through the second current steering circuit.

Switched current-steering digital transmitter with encoder based up-conversion

According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Adjustable low-pass filter in a compact low-power receiver

Embodiments of a four-port isolation module are presented herein. In an embodiment, the isolation module includes a step-up autotransformer comprising a first and second winding that are electrically coupled in series at a center node. The first port of the isolation module is configured to couple an antenna to a first end node of the series coupled windings. The second port of the isolation module is configured to couple a balancing network to a second end node of the series coupled windings. The third port is configured to couple a transmit path to the center node. The fourth port is configured to couple a differential receive path across the first end node and the second end node. The isolation module effectively isolates the third port from the fourth port to prevent strong outbound signals received at the third port from saturating an LNA coupled to the fourth port.

RF front-end with wideband transmitter/receiver isolation

A circuit for a low-loss duplexer with noise cancellation in a receive (RX) path of a transceiver includes a duplexer, a balancing network, and a noise cancellation circuit. The duplexer circuit is coupled to an antenna of the transceiver. The balancing network is coupled to the duplexer and provides an impedance matching an impedance associated with the antenna. The noise cancellation circuit senses a noise signal generated by the balancing network and uses the sensed noise signal to improve a signal-to-noise ratio (SNR) of the RX path.

Low-loss electrical balance duplexer with noise cancellation

A transceiver circuit including a digital-to-analog converter, a filter coupled to the digital-to-analog converter, a passive mixer coupled to the filter, via a buffer and a multi-stage power amplifier coupled to the passive mixer via a passive amplifier. A transmitter and method for amplifying a RF signal for transmission are also provided.

Repartitioned transceiver using silicon-on-insulator

An RF front-end with on-chip transmitter/receiver isolation using a gyrator is presented herein. The RF front end is configured to support full-duplex communication and includes a gyrator and a transformer. The gyrator includes two transistors that are configured to isolate the input of a low-noise amplifier (LNA) from the output of a power amplifier (PA). The gyrator is further configured to isolate the output of the PA from the input of the LNA. The gyrator is at least partially or fully capable of being integrated on silicon-based substrate.

RF front-end with on-chip transmitter/receiver isolation using a gyrator

A circuit for a receiver with reconfigurable low-power or wideband operation may comprise one or more main signal paths each coupled to a first port and including a low-noise amplifier (LNA) configured to provide a radio frequency (RF) signal to a main mixer circuit. An auxiliary signal path may be coupled to a second port. The auxiliary signal path may include an auxiliary mixer configured to provide an on-chip matching input impedance that may match an impedance of the antenna. The first port may be coupled to an RF antenna through an off-chip matching circuit, when a low-power operation is desired. The first port may be coupled to the second port and to the RF antenna, when a wideband operation is desired.

Receiver architecture for a compact and low power receiver

A radio front end includes a duplexer, a tunable balancing network, a detector module, and a processing module. The duplexer is operably coupled to an antenna and is operable to provide electrical isolation between an outbound wireless signal and an inbound wireless signal. The tunable balancing network is operably coupled to the duplexer and operable to establish an impedance that substantially matches an impedance of the antenna based on a tuning signal. The detector module is operable to generate an error signal based on an electrical performance characteristic of the duplexer. The processing module is operable to generate the tuning signal based on the error signal.

Front end module with active tuning of a balancing network

A power distributing duplexer system is provided. In some aspects, the system includes a duplexer configured to couple an antenna to a transmitter and a receiver. The system also includes a balancing network coupled to the duplexer. The balancing network includes a network impedance. The balancing network is configured to adjust the network impedance to match an antenna impedance of the antenna. The balancing network includes a plurality of balancing network modules coupled to the duplexer. Each of the plurality of balancing network modules is configured to receive a portion of an output voltage from the duplexer.

Power distributing duplexer system

An adaptive cancellation circuit and method are provided. The circuit includes a main path and an auxiliary path. The main path includes a first amplifier configured to output a first amplified signal to a first mixer. The main path is configured to output a first signal comprising a wanted signal component and a distortion component. The auxiliary path includes a second amplifier configured to output a second amplified signal to a second mixer. The second mixer is connected to a filter configured to remove the wanted signal component. The auxiliary path is configured to output a second signal including the distortion component.

Method and apparatus for adaptive cancellation of distortion and phase noise

A circuit for a low-power and blocker-tolerant mixer-amplifier stage may include a complementary mixer formed by transmission gates having complementary structures. The complementary mixer may be configured to receive one or more radio-frequency (RF) signals and to convert the one or more RF signals to intermediate frequency (IF) current signals. A complementary TIA may be coupled to the complementary mixer and may be configured to receive the IF current signals and provide IF voltage signals. The complementary TIA may be formed by coupling an NMOS-TIA and a PMOS-TIA to a common load. A first portion of the complementary mixer may be coupled to the NMOS-TIA and a second portion of the complementary mixer may be coupled to the PMOS-TIA.

Growing community of inventors

Aliso Viejo, CA, United States of America

Mohyee Mikhemar